Special Report
Stresses In Chips Affecting Reliability At Advanced Nodes
Thermal mismatch in heterogeneous designs, different use cases, can impact everything from accelerated aging to warpage and system failures.
Top Stories
Challenges With Adaptive Control
Systems are becoming more attuned to their operational environment, but this adds many questions and issues that need to be resolved.
Improving Chip Efficiency, Reliability, And Adaptability
Fraunhofer IIS EAS’ director maps out a plan for the next generation of electronics.
Variability Becoming More Problematic, More Diverse
Increased density, heterogeneous designs, and longer lifetimes make it critical to reduce variation early in the design process.
3D-IC Reliability Degrades With Increasing Temperature
Electromigration and other aging factors become more complicated along the z axis.
Blogs
Siemens EDA’s Anthony Mastroianni and Gordon Allan explain why achieving the full potential of 3D-IC requires front-end design approaches that enable evaluation of different microarchitectures, in Ready, Set, Go: Outrunning Moore’s Law With 3D-IC.
Fraunhofer IIS EAS’ Andy Heinig contends that chiplets are a better choice for many applications than monolithic designs, in Edge AI And Chiplets.
Rambus’ Frank Ferro warns that AI and ML are stretching current data center memory infrastructures to their limit, in Boosting Data Center Memory Performance In The Zettabyte Era With HBM3.
Quadric.io’s Steve Roddy observes that fallback is a dirty word, in Don’t Let Your ML Accelerator Vendor Tell You The ‘F-Word’.
Arm’s Neil Fletcher presents technical capabilities that could make smartphones appealing but still affordable for consumers in emerging economies, in Bridging The Digital Divide With Ultra Low-Cost Smartphones.
Synopsys’ Pavani Jella warns that finding SIPI problems in the bring-up lab is far too late, in Ensuring Signal And Power Integrity In Today’s High-Speed Designs.
Cadence’s Paul McLellan shows why routing is a primary bottleneck in laying out today’s advanced packages, in Advanced Auto-Routing For TSMC InFO Technologies.
Ansys’s Kelly Damalou discusses modeling advanced process features to improve the precision of simulation results, in Facing Off Against Growing Chip Design Complexity.
Sponsor White Papers
Holistic Die-To-Die Interface Design Methodology For 2.5-D Multi-Chip-Module Systems
Energy/bit optimization approach for multi-chip systems with possibility of co-optimization with the routing resources defined by the signaling pitch.
12 Ways To Elevate Electronic Design Process Using PADS EBook
What else you can do with a PCB design.
Physics-Based Radar Modeling: Driving Toward Increased Safety
How can automotive engineers quickly and confidently verify the reliability of radar-based sensors?
Tensilica DSP Code Generation Toolbox With MATLAB/Simulink
This paper describes the features of the HSP developed for Cadence Tensilica processors and provides an example performance report obtained using the HSP for the Tensilica processor.
Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes
A simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains.
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