Advanced Auto-Routing For TSMC InFO Technologies

Routing is a primary bottleneck in laying out today’s advanced packages.


At the recent TSMC OIP Symposium, John Park presented ‘Advanced Auto-Routing for TSMC InFO Technologies.’ InFO stands for “integrated fanout” and is the lower performance, lower complexity technology for advanced packaging. For details of TSMC’s whole packaging portfolio, see my post TSMC OIP: 3DFabric Alliance and 3Dblox. Here’s the slide TSMC presented from that presentation on InFO. As you can see, InFO comes in a number of different flavors.

The first implementation, back in 2016, was InFO-PoP for mobile, adding a DRAM package on top of the application processor die. Then InFO_oS for HPC, allowing multiple die to be put in increasingly large packages. The latest technology, InFO_3D allows logic to be stacked vertically on logic, with routing underneath to distribute the power delivery network and signals.

I won’t reiterate all the arguments in favor of using advanced packaging rather than simply scaling and putting everything in the most advanced node. We’ll just take that as a given in this post. For John’s longer exposition on this topic, see my post EDPS: When Chips Become 3D Systems and the Challenges of 3DHI.

As I’ve said before, advanced packaging and heterogeneous integration have become the hottest area in all of semiconductor design today.

Routing has become the primary bottleneck

The table above shows how much more challenging routing has become. On the left are the requirements for flip-chip ball-grid-array (FCBGA). There are, at most, a few thousand connections. There is RDL signal routing to spread out the signals to the solder balls from the comparatively small single die.

On the right is the technology we are talking about today, 3D heterogeneous integration wafer-level packaging, or 3DHI-WLP. The package typically contains multiple chiplets, perhaps tens of thousands of signal connections, so the RDL signal routing is not just distributing the signals but also handling the chiplet-to-chiplet routing too. Power routing is another complication with a number of feasible approaches.

Diving down to another level of detail, among the challenges are:

  • Chiplet-to-chiplet and fanout RDL routing requirements
  • Efficient pin-escape patterns
  • Routing channel density
  • Complex via stacking
  • Interconnect fillets for yield improvement
  • Routing signals and power nets together for optimal density
  • Reuse support for repeatable patterns
  • Power/ground via placement

To address these challenges, Cadence and TSMC have been working together to develop next-generation automatic signal routing solutions for InFO technologies:

  • Multi-threaded automated routing engine for high-capacity design support
  • Routing that supports TSMC’s electrical, physical, and yield rules
  • Support for shielding, differential signals, and fillet/teardrop insertion (see below)
  • Pre-seed escape routing with reuse structures
  • Slice-based routing to support replication

The automatic power routing solution:

  • Mix and match IC-style and BGA-style power routing (stripes/rails and planes)
  • Locking structures to prevent changes when working on neighboring areas
  • Savable configurations for use in subsequent designs
  • Automatically define shape boundary styles (puzzle pieces) based on power-pin groupings

Putting it all together, the flow is:

  • Topology routing
  • Escape routing
  • Power routing
  • Detailed routing
  • Pattern replication
  • Fillet insertion
  • Final DRC


As you can see from the above tables, the speedups are impressive (factors of over 100). And using multi-threaded detailed routing with lots of cores also results in speedups of over 10X.


  • The primary bottleneck for laying out today’s advanced packages is routing
  • This applies both to signal routing (RDL/D2D) and power routing
  • A next-generation solution is required to reduce the bottleneck and support large designs
  • Cadence and TSMC have partnered to develop next-gen signal and power auto-routers for InFO packaging technologies
    • Natively massively parallelized
    • Combines multiple routing techniques
    • Portable multi-layer routing engine, Cadence’s Allegro ICP
    • Support of replication
    • Support of TSMC routing constraints and DRC rules

Leave a Reply

(Note: This name will be displayed publicly)