Top Stories
Tunnel FETs Emerge In Scaling Race – With voltages possibly below 0.5 volts, TFETs are a serious contender for ultra low-power applications at 5nm.
Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate-all-around; and nanowires. But suddenly, momentum has started building for another emerging candidate: the tunnel field-effect transistor (TFET).
From DFM To IFM – Integration for manufacturability has placed a bull’s-eye on how IP is used, and misused, in SoCs.
For the past decade the bridge between design and manufacturing was called, appropriately enough, design for manufacturing. But starting at 28nm and increasing with each successive node from there, the onslaught of IP—both third-party and internally developed—has created an integration challenge that requires some significant changes and new collaboration from both sides of the flow.
What’s After 10nm? – New materials and architectures are in research all the way down to 3nm, but the big question is how much savings future scaling will offer. Design and manufacturability may be the big sticking points.
For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions.
Collaborate Or Go Home – Semiconductor architecture is easy. It’s the exotic materials that bring complexity, cost and the need to collaborate, not to mention new ways of doing business.
The financial risk of gambling with technology and making the wrong choice has gotten so big that no one company can go it alone.
Momentum Builds For Monolithic 3D ICs – There are still problems to solve, but doing things the old way by shrinking every node may prove economically impractical.
The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit.
Leti Outlines FDSOI And Monolithic 3D IC Roadmaps – Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti.
Blogs
On The Mark: ARMing Intel – The industry has kept a close eye on Intel’s foundry business. The question is whether Intel will merely dabble in the business or become a major player.
Mentor Musings: The Trouble With Triples Part 1 – Why is this beginning to resemble a Star Trek episode?
Cascade Effects: Crunch Time – The network as we’ve known it for a couple of generations is changing before our eyes. The IoT is only the latest addition, although a very large one.
Piecing It Together: The Next Dimension – New packaging technology and stacked die are rolling out in test chips, but is this really the next big leap?
Semico Spin: IP Ecosystem Solutions For Complex Systems – As the number of unique IP blocks increases, so does the risk that something can go wrong. That can be a very expensive mistake, too.
ImPatterning: More 3D Printing Applications – Do any of these have real long-term legs; beware of the printed gun, but custom replacement organs are an interesting idea.
Viewpoints: SEMI: 3D-IC Standardization Progress Continues – There are now a total of seven published 3D standards.
Riding The Silicon Rapids: What Color Is That LED? – Measuring the spectrum is simple enough, but perception by the human eye is another matter.
Whitepapers
Improve Logic Test With A Hybrid ATPG/BIST Solution – A debate has been underway about which is better, automatic test pattern generation or built-in self-test. For some designs, combining both is better than either one alone.
