The Next Dimension

New packaging technology and stacked die are rolling out in test chips, but is this really the next big leap?


It’s hard to say definitively whether this is a trend or an aberration, but after what appears to have been a slam-dunk sprint to the finish line with finFETs some companies are re-evaluating their alternatives based upon return on investment.

In place of perpetually shrinking features—and looming multipatterning at the next node—there is renewed interest in staying at 28nm with FDSOI, moving to 2.5D with or without interposers, and something in-between such as fan-out approaches.

How much of this is real, and how much is just testing out chips, is unknown. So far, decisions aren’t finalized. The cost of any of these moves is significant, and the investment in training and technology—particularly fab equipment—is enormous. But there is one big difference between 28nm and finFETs on one side, and stacked die on the other. With the former, a chipmaker’s internal business structure doesn’t change. With the latter, there needs to be buy-in from the top down because the cost centers inside of chipmakers have to be looked at as a whole, not as discrete parts of a corporate balance sheet.

The existing flows of technology, from architecture to RTL to verification, test, signoff and manufacturing are extremely well established. They’ve been in place for decades. While the flows don’t actually need to change that much for any of this technology, how the costs get calculated will change significantly. And so will some of the business methodologies and strategies for reuse, because in fan-outs and 2.5D components can be mixed regardless of what node they were developed at, test is simpler, and overall NRE and mask costs are lower. So, too, is the equipment used to manufacture some of these components.

But amortizing that cost across the design flow, which in some cases means multiple IP and software providers, isn’t so simple. And inside big companies, changing processes such as accounting isn’t trivial. It takes money and time—sometimes as much as a couple years—to get everything running smoothly again. Add to that a lack of trailblazers in this area, with many companies waiting for someone else to do it first, and the timing gets even fuzzier.

But interest is definitely rising as chipmakers look toward inevitable changes. What exactly those changes will entail, and when they unfold, is uncertain. But changes are coming nonetheless, and they won’t just be a continuation of the same approaches that have been used since chipmakers broke the 1 micron barrier. Yield alone will force some new tactics. Physical effects will force others. And rising complexity will force still others.

We are standing on a precipice with plenty of rope, expensive bridge-building equipment, helicopters, slick new lodging on both sides, and a long trail that eventually leads to the other side. What’s the best option?