Special Report
FinFET Rollout Slower Than Expected
It costs nearly three times more to design a finFET-based chip than a 28nm planar chip, and it takes more than twice as long to get working silicon.
Top Stories
New Patterning Paradigm?
Selective deposition may be the way forward to the far reaches of device scaling after 7nm.
FD-SOI vs. FinFETs
Experts at the table, part 1: Why is FD-SOI needed and for what applications? Plus, how difficult is the transition to forward and reverse biasing and why is it important?
Next EUV Challenge: Mask Inspection
EUV lithography is making progress finally, but there are other related issues that still need to be solved.
Flash Dance For Inspection And Metrology
3D NAND is the logical next step, but metrology and inspection issues continue to mount.
Blogs
Editor in Chief Ed Sperling digs into what multi-patterning really means for the cost of developing and manufacturing at the most advanced nodes, in Big Changes At 10nm And Beyond.
Executive Editor Mark LaPedus looks at a handful of less-visible but important manufacturing trends, in 5 Issues Under The Foundry Radar.
Mentor Graphic’s David Abercrombie provides a laundry list of everything you need to know, for now, about error visualization in triple patterning, in Are Three Eyes Better Than Two?
Semico Research’s Jim Feldhan anticipates 9% revenue growth in 2015, in Predictions For A Good Year.
SEMI’s Bettina Weiss looks back on the revolution and evolution of semiconductor manufacturing, in 50 Years Of Moore’s Law.
White Paper
Faster Time To Root Cause With Diagnosis-Driven Yield Analysis
Methods for understanding how and why chips fail and how to improve yield.
