Big Changes At 10nm And Beyond

What does multi-patterning really mean for the cost of developing and manufacturing at the most advanced nodes? We’re about to find out.


The move to 16/14nm finFETs is relatively straightforward. The move to 10nm and 7nm will be quite different.

While double patterning with colors at 16/14nm has a rather steep learning curve, reports from chipmakers developing advanced chips is the technology and methodologies are manageable once engineering teams begin working with it. The hardest part is visualizing how different parts will be layered together across multiple masks, but once engineers put their trust in tools that have been developed to deal with this, it appears to work just fine.

There are big benefits to moving to finFETs, particularly in high-performance applications. Leakage current has been noticeable since 90nm and problematic since 65nm. And while FD-SOI has solved the problem at 28nm, companies that need density and high performance must move to the next process node if they want to stay in a planar architecture. Moving to finFETs at 16/14nm is an evolutionary improvement with minimal disruption to the design through manufacturing flow, and it brings a proven reduction in leakage current because there is better control of the gate.

In fact, the big challenge with 16/14nm finFETs isn’t leakage. It’s learning to live with a sharp increase in dynamic current, and being able to manage thermal differences in confined spaces. The temperature is different at the bottom of tightly packed fins than at the top, which can have an effect on reliability over time and signal integrity at intervals when there are heavy compute workloads.

The move to 10nm is a whole different story. Moving from double patterning to multi-patterning is many times more complicated. David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics, explains that problem No. 1 is that the basic representation of the graphs in the tools is planar, but the problems being addressed may be 3D rather than 2D. Second, if you color every polygon as they are drawn—which is what design engineers would expect to do—the colors may be wrong. But going back and fixing colors as changes are made would be a nightmarish. Tools and methodologies will have to be updated across the board. The challenge is that at 10nm and beyond the tools, the process and the design flow are all more interdependent, and a change in any one will affect the other two. That’s particularly troublesome when you’re dealing with version .01 of a new process and the increasingly complex tools and methodologies need to be updated in sync with that.

Making matters worse, there’s a question of whether foundries will opt for triple patterning or quad patterning, which is essentially double-double-patterning. The likelihood is there will be a mix, depending upon the foundry, meaning design approaches would become foundry-specific. Abercrombie says heuristics also will be necessary to make all of this work or it will take the rest of your life to color more than 30 polygons correctly—basically betting on probabilities with little history to prove them right or wrong.

Next-generation lithography options might help significantly. So might different packaging and architectural approaches, including 2.5D and 3D. But no matter what approaches ultimately are adopted by the semiconductor industry, what comes after 16/14nm is going to be much more difficult than the move from 28nm to 16nm/14nm if you’re drawing anything but perfect rectangles. And even those will become more difficult to design and manufacture.

It’s certain that power and performance will continue to dominate decisions at the leading edge of design. Power will continue to be a gating factor, which is why we have multicore processors and many-processor designs. But as complexity on the manufacturing side continues to rise and spills over into other areas, cost also will begin surfacing as a critical discussion point even in price-insensitive applications such as servers or networking hardware. At this point no one knows just how difficult this is going to become, which means no one is certain of just how high the price tag will go.