Special Report

EUV: Cost Killer Or Savior?
There’s no such thing as a simple cost decision with EUV at its current power level.

Top Stories

Finding Defects Is Getting Harder
If the current inspection technology runs out of steam at 10nm, what will take it’s place?

Mask Supply Chain Preps For 10nm
Technology generally on track, but not everything is ready.

ALD Market Heats Up
Number of applications for technology increase, and so do the number of companies vying for a piece of the growing market.

Blogs

Editor in Chief Ed Sperling observes that questions about how to build future chips fall into three camps, in Raise A Fence, Dig A Tunnel, Build A Bridge.

Executive Editor Mark LaPedus talks with Everspin’s top exec about where next-gen memory is heading, in Inside The MRAM.

KLA guest blogger—IMEC Fellow Guido Groeseneken—examines the tradeoff between more scaling and upsetting a finely-tuned ecosystem, in We Must Teach Chips To Feel Pain.

Mentor Graphics’ Jeff Wilson looks at why CMP modeling was so slow to catch on and what’s changed, in Déjà Vu For CMP Modeling?

SEMI’s latest report shows that SiP and stacked die are generating lots more buzz as scaling becomes more difficult, in SEMICON Taiwan’s Packaging Punch.

Semico’s Jim Feldhan finds that maximizing performance and minimizing costs will require much more industry-wide collaboration, in New System Requirements Demand A Creatively Orchestrated Ecosystem.

Sponsor White Paper

DFM-Compliant IP: Why You Need It, How You Get It
How to improve yield even when designs contain externally developed IP.