Mask Supply Chain Preps For 10nm

Technology generally on track, but not everything is ready.


As the semiconductor industry gears up for the 10nm logic node—now likely to begin in the second half of 2017—the photomask supply chain is preparing to grapple with the associated challenges, including dramatic increases in photomask complexity, write times and data volumes.

The 10nm node will require more photomasks per mask set, the ability to print smaller and more complex features, heavier use of reticle enhancement technologies (RETs) such as optical proximity correction (OPC) and more computational power for distributed model-based data preparation.

The good news is that the technology required appears mostly on track. But there are still plenty of kinks to work out.

Franklin Kalk, executive vice president and chief technology officer at merchant photomask supplier Toppan Photomasks, gives generally high marks to the state of the industry’s preparedness for delivering the materials, mask data preparation (MDP), mask writing, inspection and repair capabilities required for 10nm. “The 10nm logic process is defined already,” Kalk said. “The work remaining to be done is yield improvement.”

Linyong (Leo) Pang, executive vice president and chief product officer at computational design platform supplier D2S, agrees. “Overall, using new technologies, mask makers should be able to handle the 10nm mask patterns,” Pang said. Some of the technology required is already deployed at leading customers and some is already being used in production, he added.

Lengthening Write Times
The biggest challenges for mask makers at the 10nm node are the addition of triple and quadruple patterning and the growing complexity of the mask features, including curvilinear shapes. Both of these challenges contribute to the overriding problem facing the photomask industry at 10nm and beyond: longer mask write times. According to Sematech, mask write times have increased by about 25% per year since 2011. The number of masks in a mask set—and the percentage of critical layers in each mask set—are also growing.

“Write times are beginning to stretch a bit,” Kalk said. He added that the increased use of one-dimensional gridded design rules helps to mitigate the increased write times required for leading-edge masks. “But,” he said, “scaling math is still reality.”

Double patterning, which involves splitting the layout of a chip’s critical layers among two photomasks, has been used by the semiconductor industry since the 20nm node to extend the life of 193nm immersion lithography. Smaller feature sizes and tighter pitches at 10nm mean that some critical layers will require triple and even quadruple patterning. “You are forced to do more multi-patterning decomposition into more and more layers so that you can image these things,” said Michael White, director of product marketing for Calibre Physical Verification at Mentor Graphics.

While most of the masks in a mask set continue to be written by comparatively fast laser writing tools, a growing number of critical layers need to be written with e-beam mask writers, which offer better resolution and critical dimension control, but have much longer write times. According to a paper presented by Intel’s Frank Abboud and several colleagues at the SPIE Photomask Technology Conference last year, the percentage of layers in a mask set that require an e-beam writer increases by nearly 10% from the 14nm node to the 10nm node.

The photomask industry continues to wait on the arrival of muti-beam e-beam mask writers, which have been in development for several years. Multi-beam tools promising dramatic improvements in write times are being developed by IMS Nanofabrication in conjunction with JEOL and by NuFlare. But those tools are not expected to be available in time for the 10nm logic node. (A beta version of the IMS/JEOL tool is expected to ship this year, with the first high-volume manufacturing tool expected to follow next year. But those tools are now targeted at the 7nm node.)

Kalk believes single-beam e-beam tools will need to continue to handle the workload at the 10nm node and at least the beginning of the 7nm node.

With multi-beam tools not available for 10nm, Pang said mask makers will continue to focus on reducing e-beam shot count to keep write times in check. One technique, the use of overlapping shots, can cut mask writing times by as much as 50%, Pang said. Using overlapping shots requires model-based MDP to simulate the interaction between the mask writer and the mask.

Several other techniques will be used to reduce total shot count at the 10nm node, including optimization of the MDP fracturing step and other techniques employed during RET implementation. Steffen Schulze, marketing director for Mentor Graphics’ Calibre Semiconductor Solutions, said these techniques can reduce total shot count by as much as 40%.

Move to Model-based MDP
Adoption of model-based MDP is widely considered to be critical at the 10nm node, in part because the mask shapes are so small that their proximity to each other has a major impact on the ability to print them on a mask.

“Most of the mask shops are looking for things like mask error correction and shot optimization,” said Anjaneya Thakar, a product marketing manager in Synopsys’ Silicon Engineering Group. “And they realize that to do those two things efficiently and meet accuracy requirements, you have to rely on model-based MDP. They aren’t happy about it, because now they have to do all the model calibration and model generation stuff. But they know that they will have to get there at some point.”

At 10nm, the introduction of inverse lithography technology (ILT) and use of more aggressive OPC being deployed to meet process window specifications for some critical layers will add to the complexity of the mask data, increasing the time needed for MDP, Thakar said. The fractured data file size for a complete 10nm mask set is projected to be about 4X what it was at the 14nm node, according to the SPIE paper presented by Intel researchers.

Model-based MDP requires more time and computing power than old school MDP methods. However, mask shops have beefed up their computational resources over the years, Thakar said, to the point where captive mask shops at IDMs now have “plenty of horsepower” to do model-based MDP and the advanced mask shops of merchant mask makers also have 100s of CPU cores available.

“Model-based data preparation is still immature, so the computational loads are not as onerous as some people have predicted,” said Kalk, who characterized MDP as “in good shape” for the 10nm node overall.

Thakar said the increase in MDP time can be partially mitigated with improved software algorithms that enable distributed processing over hundreds of CPU cores and model-based fracture algorithms to optimize shot count. New fracture methods for mask error correction that use OPC-like edge adjustments can also cut write times by improving CD uniformity, Thakar said. (See reference 1)

New Inspection Technologies
Smaller feature sizes at the 10nm node also present challenges for mask and reticle inspection tools, which must detect new classes of more minute defects and identify more mask “hotspots.”

Yalin Xiong, general manager of the Reticle Products Division at KLA-Tencor, said defect inspection at the 10nm node requires new technologies to detect lithographically significant defects without being inundated by nuisance defects caused by aggressive OPC and ILT.

Pang said the decreasing size of lithographically significant mask defects is pushing the fundamental limits of inspection tools. “They [defects] look really fuzzy,” Pang said. “The defect size is actually getting smaller than the pixel size of inspection tools.”

But Kalk gives vendors high marks for delivering new inspection capabilities such as wafer-plane inspection and others that identify lithographically significant defects. He said the mask inspection technology needed for the 10nm node is largely in place. “The inspection tool suppliers have responded with increasingly sophisticated methods to keep pace with industry needs,” Kalk said.

Xiong said KLA-Tencor has been collaborating with mask shops to develop a new dual-imaging technology that can find lithographically significant defects on 10nm masks. The technology is successfully being used by leading mask shops around the world, Xiong said.

Room for Improvement
Two areas of the mask supply chain that Kalk believes need to improve before 10nm goes into production are mask materials and repair. “The mask materials still require defect improvement,” Kalk said. “Acceptable yield can be achieved with materials from more than one photomask blank supplier, but the amount of repair required varies by supplier.”

He added: “Repair tools have the accuracy required, but reliability and service must be improved.”

Reference 1: It should be noted that Synopsys relies on a CPU approach, while D2S relies on a GPU approach. 

Leave a Reply

(Note: This name will be displayed publicly)