Top Stories
EUV’s Uncertain Future At 3nm And Below
Manufacturing chips at future nodes is possible from a technology standpoint, but that’s not the only consideration.
Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
One-on-one with Lam CTO Rick Gottscho.
Compute-In-Memory Accelerators Up-End Network Design Tradeoffs
Compute paradigm shifting as more data needs to be processed more quickly.
Blogs
Editor In Chief Ed Sperling points to a surge in complexity of materials used at 5nm and beyond, in The Chemistry Of Semiconductors.
SEMI’s Heidi Hoffman walks through how to help offices recover and repopulate by identifying risks in a crisis and ensuring safety, in Best Practices In Business Continuity Planning.
Lam Research’s Steven T. Mayer, Bryan Buckalew, and Kari Thorkelsson explain how to achieve high-quality, smooth surfaces at the tops of the megapillars and uniform megapillar height across the wafer, in Fan-Out Wafer-Level Packaging And Copper Electrodeposition.
Sponsor White Papers
Super Planarizing Material For Trench And Via Arrays
A new type of planarizing material uses Marangoni effect to pull material to the dense feature area.
Consideration Of Missing Defect Suppression Technique In EUV Hole Patterning
Optimizing CD variation and defect reduction comprehensively, to improve results of a wide defect process window with a narrow CD distribution.
High-Performance 300 KW 3-Phase SiC Inverter Based On Next Generation Modular SiC Power Modules
A high-performance, low-cost, compact 3-phase inverter based on next generation power modules optimized to use third generation of silicon carbide (SiC) MOSFETs.
