Top Stories
EUV Challenges And Unknowns At 3nm And Below
Rising costs, complexity, and fuzzy delivery schedules are casting a cloud over next-gen lithography.
Bonding Challenges For Multi-Chip Packages
Disaggregation solves some problems, but it creates new ones.
What’s Next In AI, Chips And Masks
The impact of deep learning and new technology on scaling to future nodes.
Blogs
Executive Editor Mark LaPedus wonders if price increases are in store for wafers, in Upturn Seen For Silicon Wafer Market.
Quik-Pak’s Sam Sadri describes how to reduce handling and predict failures, and provides tips for dealing with complex packaging technologies, in The Ten Commandments Of Packaging.
Amkor’s Vineet Pancholi addresses test challenges in leading IC markets such as 5G, AI, and automotive, in Taking Advantage Of Outsourced Test Services.
Lam Research’s Nerissa Draeger observes that finFETs are reaching the end of their utility as challenges mount at the 5/3nm nodes, but new transistor types are on the horizon, in From FinFETs To Gate-All-Around.
SEMI’s guest blogger Jean-Marc Philippe examines how Industry 4.0 technology is breathing new life into aging chipmaking equipment, in Smart Manufacturing In Fabs.
