Rising costs, complexity, and fuzzy delivery schedules are casting a cloud over next-gen lithography.
The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up.
In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV products. For example, ASML is developing new EUV scanners, including a next-generation system with a staggering price tag of more than $300 million per unit. So far, it’s unclear if these systems will arrive on time.
Today, meanwhile, Samsung and TSMC already are using current-generation EUV in production at 7nm and 5nm, and Intel is preparing to deploy it for the first time. Situated in a fab, an EUV lithography scanner patterns features on chips at 13.5nm wavelengths. EUV and other equipment help chipmakers to reduce the feature sizes in chips at each node, enabling more transistors to be packed on a die.
Samsung and TSMC are preparing to use EUV for 3nm, which is slated for 2022, as well as for 2nm production following that. In addition, DRAM vendors are moving EUV into production at the 1nm nodes. Beyond that, the future is cloudy. Bringing up next-generation EUV technology is a huge task.
On the device side there is uncertainty about just how much longer chip scaling will continue, and how quickly it will happen. A 1nm node is on the roadmap, but it’s not clear at this point how realistic that is. It’s possible that the industry will enable scaling at 1nm and beyond, but chipmakers also are hedging their bets with advanced packaging options.
They also are pushing ahead with the next phase for EUV. Among the developments:
New EUV scanners
In a generic process flow, a chipmaker designs an IC, which is translated into a file format. Then, in a photomask facility, a mask is produced based on that format. The mask is a master template for an IC design.
In a fab, the mask as well as a wafer are inserted in a lithography scanner. A photoresist, a light-sensitive material, is applied on the wafer. In operation, the scanner generates light, which is transported through a set of projection optics and the mask in the system. Light then hits the resist, creating patterns on the wafer.
For years, chipmakers used optical-based 193nm wavelength lithography tools to pattern the advanced features in chips. With multiple patterning, chipmakers extended 193nm lithography down to 7nm. But at 5nm, it’s too complex to use these techniques.
“In principle, you could do things with optical lithography,” said Harry Levinson, principal at HJL Lithography. “But if you just counted up the number of masking steps to try to do, say, a foundry 5nm node, it was over 100 masking steps. And that isn’t workable for many reasons.”
That’s where EUV fits in. After years of delays, EUV lithography is finally in production. EUV simplifies the process and enables chipmakers to pattern the most difficult features at 7nm and beyond. Today, chipmakers are in production using ASML’s latest EUV scanner, the NXE:3400C. Incorporating a 0.33 numerical aperture (NA) lens with 13nm resolutions, the system has a throughput from 135 to 145 wafers per hour (wph).
EUV is complicated. In operation, laser pulses are generated. In the system, the pulses hit tiny tin droplets at high speeds, creating photons. Photons bounce off several mirrors within the scanner. Then, photons reflect off the mask and onto the wafer for patterning.
EUV works, but this process can sometimes cause stochastics, or unwanted variations. If there is a mishap during the process, EUV can cause stochastic-induced defects in chips.
During the EUV process, particles can land on the mask, causing print-induced defects on the wafer. This is why chipmakers want pellicles, which are thin membranes that cover and protect the masks. But EUV pellicles still aren’t ready, and chipmakers have moved into production without them.
Uptime is another issue. The latest 193nm scanners have a throughput up to 295 wph without downtime. The average uptime for EUV is 84%, but 90% and above is commonplace. “Both average and the variation need to be improved further,” said Eric Verhoeven, product manager of ASML, in a recent presentation.
Nonetheless, in 2018, ASML’s 0.33 NA EUV scanners were inserted for production at 7nm. At 7nm, chipmakers are using EUV to pattern chip features with pitches starting at 40nm.
Vendors are using an EUV-based single patterning approach. The idea is to put the chip features on one mask and print them on the wafer using a single lithographic exposure.
Chipmakers want to extend EUV single patterning as far as possible, because it’s a straightforward process. EUV single patterning reaches the limit at 32nm to 30nm pitches, which represents the 5nm node or so.
At those pitches and beyond, roughly at the 3nm node, chipmakers need to look at new options. The first option is EUV double patterning. For the second option, ASML is developing a high-NA EUV scanner, which is a completely new system. Still in R&D, ASML’s high-NA EUV system features a new 0.55 NA lens capable of 8nm resolutions.
But the high-NA system is complex and expensive, and bringing up a new tool in the fab presents some risks. Moreover, the system won’t be ready for the initial phases of 3nm in 2022. High-NA is expected to move into production in 2024.
So chipmakers may have little choice but to deploy EUV double patterning. In double patterning, you split the chip features on two masks and print them on the wafer. That’s complex and expensive, but it’s also something the fabs have mastered because EUV was delayed for so long.
“This is similar to what has been done with 193nm immersion with multiple patterning,” said Doug Guerrero, senior technologist at Brewer Science. “Without a doubt, this will be the first path for EUV. There are groups already working on EUV multiple patterning strategies. In addition, progress will not be a linear progression from the past.”
EUV double patterning requires more process steps in the fab, which impacts the throughput of the scanner. Therefore, chipmakers need faster EUV systems. In response, ASML has two more 0.33 NA EUV scanners on its roadmap. These upgraded systems are faster versions of the current scanners.
The first system, called the NXE:3600D, has a throughput of 160 wph. This tool is slated for mid-2021. The next tool has a throughput of 220 wph, and is scheduled to roll out in 2023.
At some point, EUV multiple patterning will become too complex. That’s why chipmakers are pushing for high-NA EUV at 3nm and beyond. This will enable them to revert back to the simpler single-patterning approach. “High-NA reduces process complexity,” said Jan Van Schoot, a senior principal architect at ASML. “Total patterning costs are reduced by more than 10% and wafer cycle time over 20% (by) removing multiple exposures.”
The first high-NA tool, called the EXE:5000, has a throughput of 185 wph and is slated for 2022. ASML has added a new high-NA system to the roadmap. The EXE:5200 is a faster version slated for 2024.
High-NA is different than the current EUV scanners. Instead of a traditional lens, the high-NA tool incorporates an anamorphic lens, supporting 8X magnification in one direction and 4X in the other. So the field size is reduced by half. In some cases, a chipmaker would process a chip on two masks. Then the masks are stitched together and printed on the wafer, which is a complex process.
Moving high-NA into production is a monumental task. “Regarding the challenges, the short answer is everything,” Brewer Science’s Guerrero said. “In my view, maybe the traditional resist on a multilayer stack approach might not even be the method for patterning. New resistless processes might be required. Cost is another issue. If five people can afford EUV now, how many will be able to pay for high-NA tools?”
A high-NA scanner will cost roughly $318.6 million per system, compared to $153.4 million for today’s EUV scanners, according to KeyBanc.
New resist processes
Besides the scanner, it’s also important to look at the other parts of the EUV ecosystem, namely the photoresists and how to deposit them on a wafer.
This takes place before the patterning process. In the flow, wafers are inserted into a system called a coater/developer. The system pours photoresist materials onto a wafer. The wafer is spun, causing the resist to cover the wafer.
From there, the wafers are transported to a lithography scanner for patterning. Then, the wafers are moved to other equipment in the fab for processing.
Fig. 1: Example of a typical sequence of lithographic processing steps. Source: Chris Mack, Fractilia
Nonetheless, EUV resists are based on two technologies — chemically amplified resists (CARs) and metal oxide. EUV resists work at the current nodes, but there is room for improvement.
“The current baseline in 0.33 NA EUV exposure is organic CARs. Organic resists suffer from resist blur, which limits the resolution of images provided by the scanner. Simply put, the organic resists are unable to capture the inherently better photon patterns provided by today’s EUV scanners, and are far from even the lowest resolution use cases for high-NA EUV,” said Richard Wise, technical managing director at Lam Research. “Spin-on metal oxide materials have demonstrated for over a decade fundamentally higher absorptivity and improved resist blur over organic CAR variants. Yet, despite this improved resolution, these materials have struggled to create systems with the appropriate stability and defectivity required for fab spin coating technologies.”
There are other issues. “The pattern defects of EUV lithography is still an issue, and its high-resolution performance has not been fully exploited. In order to further pattern shrink of semiconductors in the future, a major issue is how to reduce these defects,” said Makoto Muramatsu, a process engineer at TEL, in a recent paper. Others contributed to the work.
In the paper, TEL discussed ways to address the issues, at least in the coater/developer part of the flow. For lines and spaces using CARs, TEL described a new rinse and underlayer optimization technology. The technology enables pattern collapse prevention for improved aspect ratios. This in turn improves linewidth roughness and provides more etch margin for better pattern transfer and improved defect prevention.
There are also coater/developer issues with metal oxide resists. During the fabrication of the metal containing layer, the bevel and the bottom of the wafer can get contaminated. For its coater/developer tool, TEL developed a new technique to prevent metal contamination. A new post exposure bake (PEB) module has been developed for improved CD uniformity.
In spin coating, there are other issues. During the process, most of the resist material falls off the wafer and is wasted. There is a solution. In R&D, Lam is developing a dry resist technology, which could displace coaters/developers. In Lam’s technology, compounds are processed in a deposition system, which in turn creates a new class of metal EUV resists. Instead of spin coating, the resist is deposited on the wafers in the deposition system, which reduces resist waste in the fab.
Dry resist processes could be used for today’s EUV and high-NA. “Dry photoresist breaks the tradeoff in resolution and stability or defectivity seen with wet resists,” Lam’s Wise said. “By forming the resist in a dry process chamber shortly before exposure, we are able to focus on photosensitivity rather than stability in solution. And by processing the material in a dry environment, we are not limited by materials constraints such as viscosity and adhesion that affect wet resists. Dry photoresist allows for a wide degree of tuning in both the coating and the development process. Rather than reformulating material in a lab to be stored in solution waiting for exposure, we can modify the process onboard our tool. This allows us to independently and quickly modify characteristics such as film thickness that can be much more challenging to modify in a spin coating environment. Dry photoresist processing (coating and development) has inherently higher utilization of material than wet processes. Spin coating results in a high level of loss of material at the wafer edge whether it’s wasted resist material in spin coating or wasted solvent during wet development.”
New masks and blanks
Photomasks are another essential piece of the lithography puzzle. Today’s traditional optical masks consist of an opaque layer of chrome on a glass substrate.
In contrast, an EUV mask consists of 40 to 50 thin alternating layers of silicon and molybdenum on a substrate. This results in a multi-layer stack that is 250nm to 350nm thick. On the stack, there is a ruthenium-based capping layer, followed by an absorber based on a tantalum material.
EUV masks work for 7nm and 5nm. But at 3nm and beyond, new EUV mask types will be required. In today’s EUV masks, the absorber is a 3D-like feature that juts out on top of the mask. In operation, EUV light hits the mask at a 6° angle. The reflections potentially cause a shadowing effect or photomask-induced imaging aberrations on the wafer. This issue, known as mask 3D effects, can result in unwanted pattern placement shifts.
Fig. 2: Cross-section of an EUV mask. Source: Luong, V., Philipsen, V., Hendrickx, E., Opsomer, K., Detavernier, C., Laubis, C., Scholze, F., Heyns, M., “Ni-Al alloys as alternative EUV mask absorber,” Appl. Sci. (8), 521 (2018). (Imec, KU Leuven, Ghent University, PTB)
To mitigate these effects, the mask requires a thinner absorber. In EUV masks, the tantalum absorber is 60nm thick. You can make this thinner, but it reaches the limit at 50nm, which doesn’t solve the mask effects.
So the industry is developing two new EUV mask types – high-k and phase-shift. Still in R&D, a high-k EUV mask resembles today’s EUV masks. Instead of a tantalum absorber, the industry is exploring other materials like nickel. A thinner nickel absorber could mitigate the mask effects, but this material is difficult to work with.
Phase-shift EUV masks, also in R&D, resemble an existing EUV mask. The difference is that a so-called “low-n” material would replace tantalum for the absorber.
In phase shifting, light from the scanner hits the mask. Some but not all of that light is blocked. “The stuff it doesn’t block is out of phase with the rest of the light. You get this phase interference effect, and it gets darker. That tends to make your images a little bit better, a little steeper and a little higher contrast,” said Chris Mack, CTO of Fractilia.
Nonetheless, making EUV masks of all types is a challenging process. In mask production, the first step is to create a substrate or mask blank. Made by a mask blank vendor, the blank serves as the base structure of a mask.
Fig. 3: Fabrication of EUV mask. Source: Sematech
To make an EUV mask blank, a vendor uses an ion beam deposition system. In operation, a substrate is placed in the system. An ion beam is then generated, which deposits alternating layers of silicon and molybdenum onto the substrate base, creating a multi-layer EUV mask blank.
There are some challenges here. “As EUV progresses into mass production and higher nodes, there is ongoing demand to improve the multi-layer properties, such as EUV reflectivity, central wavelength uniformity, and depth of effective mirror plane,” said Katrina Rook, a process engineering manager at Veeco, in a paper. “A perfect Mo/Si multi-layer has a theoretical maximum reflectivity of 73%, while experimental values have not exceeded 67% to 69%. The interfacial quality between the individual Mo and Si layers is considered critical in obtaining optimal EUV reflectivity performance.”
In an EUV mask blank, Veeco found that the interfacial layers had roughness values of 80 to 90 picometers with an intermixed layer thickness of 0.5nm to 1.9nm. The roughness doesn’t affect the reflectivity, but the intermixing of the materials could cause a reflectivity drop of about 4%, according to Veeco.
There is a solution. By tuning the deposition tool, Veeco could reduce the intermixing depth by 20% to 30%. This could improve the reflectivity in the multi-layer stack by 1% to 3%.
Once the EUV mask blank is developed, it is inspected for defects using actinic and optical inspection systems. Actinic inspection uses the same 13.5nm wavelengths as an EUV scanner.
EUV mask making
Once the mask blank is made, it is shipped to the photomask vendor, where the photomask is made. A blank is patterned, etched, repaired and inspected. Finally, a pellicle is mounted on the mask.
In mask-making, the key step is patterning. A system called an e-beam mask writer creates or writes patterns on the mask based on a given IC design. The most common mask writer system is a single-beam e-beam tool, based on variable shape beam (VSB) technology. In operation, a mask is inserted in the system and electrons hit the mask in form of shots. This, in turn, patterns the mask in rectangular-like shapes.
VSB-based mask writers are the workhorse tools for patterning traditional optical masks. But EUV masks have smaller and more complex features, and VSB is too slow to pattern them.
So, the industry needs a new mask writer technology, namely multi-beam mask writers. IMS is shipping these tools, while NuFlare is developing one. These systems utilize 262,000 tiny beamlets to speed up the write times for EUV masks. The write times for multi-beam tools are constant, taking 12 hours or so to pattern all masks.
That’s not the only reason why multi-beam mask writers are required for EUV masks. “Another reason is the need for more accurate resists, particularly for EUV, but also for 193i masks for the advanced nodes,” said Aki Fujimura, chief executive of D2S. “More accurate resists are slower, meaning that it takes more energy to expose them. To make such masks fast enough to write, high energy needs to be applied in a shorter period of time, which could cause thermal issues. Multi-beam masks have fewer thermal issues because the energy for any given exposure is much more dispersed over a larger area than in VSB, and because the distribution of heat energy is much more even over time across the reticle.”
After the patterning process, the mask undergoes separate metrology, etch and inspection steps. If the mask has defects, a photomask maker can repair some or all of them using a mask repair system. There are two types of mask repair tools, e-beam and nanomachining. Both are complementary.
“Photomask repair tools must keep pace with the shrinking feature sizes of the semiconductor industry,” said Michael Waldow, product manager at Zeiss, a supplier of e-beam mask repair tools. “Another challenge is the introduction of new EUV PSM or high-k EUV photomasks.”
In an e-beam repair tool, the mask is inserted in the system. Inside the tool, an electron beam hits the defect on the mask. The beam interacts with a precursor molecule, which can repair opaque and clear defects.
For 5nm and beyond, Zeiss is developing a next-generation mask repair tool. Slated to ship in 2021, the system incorporates a new 400-volt electron-beam column. This system can repair defects down to 60nm half-pitch on masks and extrusions of 10nm and smaller. It can repair bridges, broken-line defects and compact extrusions.
Meanwhile, Bruker, a supplier of mask repair tools, is developing a next-generation nanomachining mask repair system. Basically, a nanomachining tool uses an AFM-based diamond tip to repair mask defects.
“Nanomachining and other physical repair processes will continue to be a critical part of the mask repair process for these advanced masks,” said Jeff LeClaire, director of technology and product development at Bruker. “The material independence of these processes is critical for removal of fall-on and other residual soft defect contamination as the materials properties are most often unknown. The material independence is also an advantage in addressing hard defects for new material sets, as minimal additional process development is required for effective hard defect repair.”
Conclusion
Today, EUV is in production at 7nm and 5nm. Bringing up EUV to the next nodes isn’t a simple task. A number of moving parts must come together here.
But even if everything goes as planned, EUV will remain complex and expensive at 3nm and beyond, and it’s unclear how many chipmakers can afford it. Without a doubt, it will be a select few.
Related stories
 |
 |
 |
 |
 |
 |
 |  |
Quntome tunnels not effect.when you go 3nm.