Challenges Linger For EUV

Experts at the Table: The challenges of putting EUV into production, and why DRAM will require advanced litho in the future.


Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To view part one of this discussion, click here.

SE: At advanced nodes, chipmakers for some time patterned the features on a device using traditional 193nm optical lithography scanners with multiple patterning techniques. Then, starting at 7nm, chipmakers migrated to extreme ultraviolet (EUV) lithography to pattern the most difficult features in chips. Using 13.5nm wavelengths, an EUV scanner patterns features down to 13nm. So why do we need EUV?

Levinson: In principle you could do things with optical lithography. But if you just counted up the number of masking steps to try to do, say, a foundry 5nm node, it was over 100 masking steps. And that isn’t workable for many reasons. Just consider the development cycle time. Even for the 7nm node, we could shave an entire month off a cycle of learning by using EUV lithography compared to optical lithography and multiple patterning. That’s just cycle time. And then, because we had fewer masking steps, we had better yield. That’s why people are going to EUV. I’ve heard presentations from Intel, where they’ve intimated how painful it is trying to do five masking steps to create a one metal layer and things like that with 193nm lithography and multiple patterning. It can be done. It’s just very time consuming, very painful and very expensive. At some point, EUV lithography makes a lot of sense.

SE: It has been a challenge to put EUV into production, right?

Levinson: With every new technology, there are always new cycles of learning and improvements that can be made. EUV lithography went into manufacturing at a lower level of maturity than we allowed with other technologies, but it was exactly the right thing to do. A great way to increase the cycles of learning and to accelerate the maturation of the technology is just to put it into manufacturing and bring up all the issues. Then you get people with urgency to fix them. It’s in a pretty good place right now.

Fujimura: While a lot has progressed to enable EUV to be used for production, there is still a lot that remains to be done. And a lot is happening. While today’s use of EUV focuses on layers of applications where today’s limitations are acceptable, a full realization of all of the promise of EUV requires more progress. Examples of opportunities include cost-effective defect-free mask blanks, high-transmission pellicles even for high-NA EUV, actinic or e-beam multi-beam mask inspection, and OPC (optical proximity correction) and ILT (inverse lithography technology) for EUV, including curvilinear assist features.

SE: Initially, EUV was inserted into production for advanced logic. Now, EUV is moving into DRAM production. Any issues here?

Fujimura: I see DRAM as being different in three ways. One, the patterns are regular. Two, there are extremely high volumes of wafers for one design. It’s worth it to spend time on making better masks since even a small improvement in wafer yield makes a significant difference. Three, in DRAM, and flash for that matter, the redundancy in the design allows for imperfections in manufacturing. DRAMs are also a price-competitive market. Not all DRAM makers are at the leading edge. But the DRAM makers that are pursuing the leading edge will probably need to go to EUV eventually.

SE: Today’s traditional optical masks consist of an opaque layer of chrome on a glass substrate. EUV masks are different. The first step is to make an EUV substrate or mask blank, which consists of 40 to 50 alternating layers of silicon and molybdenum on top of a substrate, resulting in a multi-layer stack that is 250nm to 350nm thick. On the stack, there is a ruthenium-based capping layer, followed by an absorber based on tantalum. What are some of the issues here?

Figure 1: Cross-section of an EUV mask. In EUV, light hits the mask at an angle of 6°. Source: Luong, V., Philipsen, V., Hendrickx, E., Opsomer, K., Detavernier, C., Laubis, C., Scholze, F., Heyns, M., “Ni-Al alloys as alternative EUV mask absorber,” Appl. Sci. (8), 521 (2018). (Imec, KU Leuven, Ghent University, PTB)

Levinson: EUV mask blanks are going to be part of development for quite a while. There is still insufficient yield with mask blanks that have extremely low defects. EUV lithography was introduced for contact layers and via layers. It was fairly resilient in having some residual defects on the mask blank. Now we are trying to pattern metal layers. It’s a different story. You need significantly fewer defects. So the suppliers that are trying to make EUV mask blanks will continue to want to get their yields up. At the recent SPIE Photomask event, we heard several papers on the subject of mask blanks. We have the development of a high-k absorber and attenuated phase shifting absorbers. These address very serious problems. And ASML is talking about the idea of a ruthenium/silicon multi-layer EUV mask. That’s something that GlobalFoundries patented a few years back, which can help with these mask 3D effects. So there are two issues here, yield and mask 3D effects. They’re both serious, and they’re going to be with us for a long time.

Kasprowicz: In the current format, we’re looking at the tantalum-based absorber. Certainly, it’s working and in production. I’m sure yields are still being improved, so the demand is maybe outweighing the supply. That’s still unclear. But at least through the current nodes, that will be the process of record for those in EUV production. It’s when you start migrating beyond what foundries are calling their 5nm node. They will start doing an additional shrink, where the 3D mask effects will take more dominance in the error factors. So that’s when things like high-k and PSM (phase-shift masks) elements will start coming into play for the EUV mask absorber. The multi-layer stack is likely not going to change for the existing 0.33 NA EUV tools. That’s more of a high-NA EUV problem. So you can improve the multi-layer performance and continue to mitigate the defects. On the absorber, though, it’s a continuous development issue. Nobody has pinpointed exactly what those materials will be for the absorber. There’s a lot of ideas. And then, the question is how long will it take them to vet those out and get them in the marketplace. The bigger question is, how many absorber versions are we going to have? Are we going to have one, two, or six? It’s kind of like what we ended up having at ArF (argon fluoride laser or 193nm lithography). Everybody had a different blank for a different layer, it seemed. In EUV, that’s likely untenable just because of the material costs, as well as all the development that’s required to meet the timing.

SE: What are 3D mask effects and what are the concerns here?

Levinson: Ideally, a mask just consists of an area that is bright and one that’s dark, and there’s a very sharp boundary between them. In the case of an EUV mask, your bright area is a reflector, which ideally is a thin layer. The truth of the matter is that the effective plane of reflection is 40 or 50 nanometers below the surface. So you have these complex interactions of the reflections from the multi- layer interacting with the absorbers. And because the absorbers are not highly absorbing, that further complicates the problem. And that can get manifested into a number of problems. If you have dipole illumination, due to mask 3D effects, the image from the right dipole is physically at a different place on the wafer than the image from the left dipole. So you put the two together and now you have a blurred image. It’s defeating the whole point of EUV, where you want good resolution. And there are many other manifestations of mask 3D effects. As far back as 2001, there is a paper from Intel showing that the plane of best focus was a function of pitch, and the range was something like 40 or 50 nanometers, which is a huge percentage of the depth of focus budget. So it’s a very complex problem. A lot of smart people are working on it. Even then, the progress is slow.

SE: In the process flow, a mask blank vendor makes a mask blank. Then, the blank is shipped to a photomask vendor where the mask is made. To pattern the features on a traditional optical-based photomask, mask makers use single-beam e-beam tools based on variable shaped beam (VSB) technology. For EUV masks, though, the industry has developed multi-beam mask writers. Why do we need multi-beam mask writers for EUV masks?

Nakayamada: We use electron beams in printing images on a glass substrate. Electron beams are shaped in various sizes of rectangles or triangles. That is why it is called variable shaped beam or VSB. VSB mask writers won’t go away as long as mature nodes exist. But right now, at the 3nm node and beyond, VSB is rapidly diminishing. On EUV masks, there are more features than optical masks because EUV can print more tiny features. The total number of VSB shots to print such tiny and dense features can go up to 6 tera in total with 4 pass writing. And so the writing time to print a single EUV mask becomes intolerably long. However, a multi-beam mask writer has typically 262,000 small beams of about 10nm to 20nm. Even if we choose a smaller 10nm beam and increase the pass count from 4 to 16 to get better placement accuracy, each beam has to print only 8 gigapixels in total compared to 6 tera for VSB. The advantage of multi-beam in both write time and placement accuracy is very obvious. Once again, the purpose is write times. If we write EUV masks using a VSB writer, the write time is two to three days maximum. But if you use multi-beam, the write time is flat. It’s 12 hours or 13 hours. That’s the fundamental difference.

Fujimura: In general, there are two reasons. Complex masks, such as curvilinear shapes, make it very difficult for a VSB machine to handle them. For multi-beam mask writers, it doesn’t matter whether it’s curvilinear or not. Given a particular resolution that you need, it takes the same amount of time to write the mask, regardless of complexity of the shapes. Another reason is the need for more accurate resists, particularly for EUV, but also for 193i masks for the advanced nodes. More accurate resists are slower, meaning that it takes more energy to expose them. To make such masks fast enough to write, high energy needs to be applied in a shorter period of time, which could cause thermal issues. Multi-beam masks have fewer thermal issues because the energy for any given exposure is much more dispersed over a larger area than in VSB, and because the distribution of heat energy is much more even over time across the reticle.

SE: EUV mask inspection is also a critical. During the EUV mask process flow, defects or particles can crop up on the reticle. If the defects aren’t found and removed, the defect image may print on the wafer, thereby impacting chip yields or causing failures. To find defects, the industry has been inspecting EUV masks using optical inspection systems. Now, actinic-based inspection tools are here. What are some of the issues here? (Actinic inspection uses the same 13.5nm wavelength as EUV to find defects.)

Kasprowicz: There are a couple of things that are driving actinic-based inspection in general. One of them is phase defects. How can you manufacture an EUV blank or mask and have some confidence that there are no phase defects? The ArF (193nm) inspection tools are able to capture the pattern defects for the most part through the 7nm node pretty routinely. They may have missed some subtle things here and there, but they have improved over time. Then Lasertec’s ABI tool came out, which is an EUV mask blank actinic inspection tool. That satisfied some or most of the patterned mask phase-defect needs. So now you hopefully have a clean EUV mask blank that satisfies that requirement. Then, in the next requirement, people thought that they absolutely needed to have a pellicle. And as we’ve learned over the course of the last 12 to 18 months, it’s all product-dependent. If you have a large single die, two die in a full mask field, then absolutely you’re going to employ a pellicle. You’re going to need that because you’re going to have a high risk of failure. It’s not only one part of the die, but the entire die could just fail and you get zero yield. When you’re running multi die per reticle, such as memory, ASICs, and other devices, you can get away with that and still manage to have good wafer yields. So that was the big driver at the onset. We needed to have through-pellicle inspection and that drove actinic-based pattern inspection, at least in the mask manufacturing facilities. Then you fast forward and all of a sudden that mask is now in the wafer fab. You still have the same problem. The large die providers still want to have actinic pattern inspection with through-pellicle. After they clean the mask, they want to come back and make sure they didn’t ruin a geometry somewhere, or that a particle didn’t get on the mask before they got the pellicle on. So they need that confidence. The lifetime of the mask is also a concern. How many cleans will the mask see, and what kind of erosion in the ruthenium capping layer before you start exposing the multi-layer? So you’re effectively changing your mirror, and you’re damaging your transmission or even damaging your absorber. You can mitigate the problem a few ways. By using a pellicle, it is assumed that fewer cleans will be required during the lifetime of the mask, and perhaps dedicating the mask to a specific tool while you run that product, similar to the way a memory fab might run.

Fujimura: Mask requalification in the wafer fab is key. After the mask is already produced and given to the wafer fab, they need to make sure that it’s still good. This is especially important if have an EUV mask without a pellicle. In the recent eBeam Initiative survey, the luminaries collectively indicated that both actinic and multi-beam e-beam inspection will be deployed.

SE: Pellicles are also important. A pellicle is a thin membrane situated on a mask that prevents particles or dust from landing on the mask. Do we need pellicles for EUV?

Levinson: It really has to do with what you’re trying to make. Right now, we’re making mostly contact and via layers with EUV. So it’s less sensitive to blank defects. It’s going to be less sensitive to add-on particles. That changes when you go to the metal layers. Then, there is a difference whether you’re a memory maker with redundancy or making logic parts. It also depends whether you have 12 chips in an exposure field versus 1. So it will depend on your business case. ASML had a paper a couple of years back on this topic. They looked at the different use cases. With a pellicle, you lose transmission, and hence, throughput of your tool. And you have to balance that against your fear of getting a particle on the mask. If you didn’t have any transmission loss, I don’t think anybody would hesitate to use pellicles. They just simplify things.

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Jtaza says:

Both Samsung and tsmc have optimized their Fabs around not using pellicles. The product mix will definitely change going forward, but it’s unlikely they will be t
robust adopters once the supply chain to figure out the challenges. Also important to know the key people in Samsung believe Advanced Medical they only extend the useful life of an EUV by 5 to 7%.

9091930 says:

EUV also causes difficulties for printing straight lines across the ring field:

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