Top Stories
The Brave New World Of FinFETs – Moving to the next process nodes is creating new opportunities and a whole new set of challenges.
Power Is A Global Issue – The Inside Track: Why power has become so important and where the big advances will be in the future.
Transient Current Crunch – Transient power noise is one of the most limiting aspects of the chip design process with package and board inductance limiting how low the supply voltage can go.
Experts At The Table: Who Takes Responsibility? – Last of three parts: Coverage issues; who’s responsible for performance degradation; warranties on IP; limitations on risk.
On-Chip MCUs Excel At Power Management – When it comes to supplying power to an SoC, there is an increasing trend to make it more intelligent. On-chip MCUs can help here.
Flexibility Improves Memory Interface Bandwidth – With memory at the heart of most SoCs today, careful design is key to achieving the best bandwidth, performance and power. Flexibility plays a big role.
Latest News
Power/Performance Bits: Oct. 8 – Using gold to examine light; wavy CNTs draw heat.
Calendar of Events – An ongoing and regularly updated look at what’s scheduled in the semiconductor industry.
Blogs
Editor’s Note: Critical Choices – The discussion about what’s good enough is shifting. Now it’s what’s good enough where.
Power Source: Reliability Challenges In 16nm FinFET Design – FinFETs are a game changer, but they create reliability problems that engineers will need to grapple with.
IP And LP In SoC: Low Power Verification – “X” Marks the Spot – Understanding X values can mean the difference between a working chip and a functional disaster.
Jasper Gold: How Secure Is Your Design? – There are limits to how effective conventional RTL validation methods can be.
Power Architect: Thermals And New Technology Nodes – How important will thermal analysis be with FinFET? All signs point to ‘very.’
Power Aware A-Z: Mobile Technology Unchained – There are several different approaches to reduce power consumption and produce a smaller, lightweight battery.
Power Awareness: Don’t Stop Listening – Lessons from a former leader.
Whitepapers
Technologies For Power, Signal, Thermal, And EMI Sign-Off For Chip-Package-PCB Designs – Conflicting design requirements require a re-examination of the traditional domain-specific design implementation and validation methodology.
HDMI 2.0 Design And Verification Challenges – A look at the new audio/video standard, how it applies to 4K ultra-HD, and what you need to know about it.
Jasper Security Path Verification – How to find paths propagating data to and from secure areas and why this is not possible with standard formal verification tools.
The Integrated IP Subsystem: A Converging SoC Solution – The next-generation consumer device will include thousands of embedded systems and subsystems to perform invisible work when called upon.
Advanced Verification IP Accelerates PCIe Integration Test – What should be included in integration test and how to get it done efficiently.
