HDMI 2.0 Design And Verification Challenges

Device degradation becomes limiting factor in IC scaling, and a significant challenge in advanced SoCs.

As cloud services adoption soars, datacenter chip requirements are evolving.

How cost-sensitive are IoT edge devices, what are the real drivers for this industry, and what is the impact on EDA and IP?

Dynamic power density and rising leakage power becoming more problematic at each new node.

In a world that favors digital circuitry, analog has increasingly had to cope with processes that have become less favorable to them. But that may be changing

Timing and variability have long been missing from automated transistor-level simulation tools. At advanced nodes, an update will be required.

Minimizing power consumption for a given amount of work is a complex problem that spans many aspects of the design flow. How close can we get to achieving the optimum?

Just relying on faster processor clock speeds isn’t sufficient for vision processing, and the idea is spreading to other markets.