Top Stories
Is UCIe Really Universal?
Why developing a multi-vendor standard for plug-and-play chiplets is so difficult.
EDA Tools For Quantum Chips
Quantum doesn’t always follow normal design rules; many unknowns remain.
The Drive Toward Virtual Prototypes
Prototypes are transforming rapidly to take on myriad tasks, but they are hampered by a lack of abstractions, standards, and interfaces.
Improving Concurrent Chip Design, Manufacturing, And Test Flows
Realizing the benefits of digital twins is more complicated than translating data between tools.
Blogs
Technology Editor Brian Bailey contends that even though standards are rarely created for the benefit of the industry, that can be a useful by-product, in The Politics Of Standards.
Siemens EDA’s Bill Acito observes that a clear-cut delineation between silicon die design and IC packaging design no longer exists, in Mastering FOWLP And 2.5D Design Is Easier Than You Think.
Synopsys’ Bradley Geden predicts that multi-die technology will be the next major advance in semiconductor design productivity, in Addressing Three Big Challenges In Silicon Realization.
Cadence’s Neil Zaman looks at the role of digital twins in reducing data center power consumption, in Effective Measurement Is The Key To Meeting Environmental Sustainability Goals In Data Centers.
Renesas’ Sailesh Chittipeddi finds that transforming data at the source of collection minimizes latency and enables optimized processing for time-critical applications, in AI At The IoT Edge Is Disrupting The Industrial Market.
Codasip’s Lauranne Choquin explains why more students should focus on electronics, in Being A Design Verification Engineer Is Fun And Rewarding.
Synopsys’ Anand Thiruvengadam and Guy Cortez show how to identify and mitigate potential failures prior to tapeout, in Ensuring Memory Reliability Throughout The Silicon Lifecycle.
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