Special Report
Missing Interposer Abstractions And Standards
Interposers still need to be opened to the masses; benefits include more flexibility and fewer aging effects.
Top Stories
Product Lifecycle Management For Semiconductors
The C-Suite wants the chip industry to use PLM, but are their issues different enough that a more specialized black-box approach would be better?
Advanced Packaging Shifts Design Focus To System Level
Partitioning and floor-planning become big challenges. What goes on which die?
Gaps In The AI Debug Process
Verification and debug of AI is a multi-level problem with several stakeholders, each with different tools and responsibilities.
Video
1.6 Tb/S Ethernet Challenges
What works, what needs to be fixed, as the complexity and volume of data continues to grow.
Blogs
Technology Editor Brian Bailey argues that system decomposition is necessary to be able to handle complexity, but thinking in the pure functional space is difficult, in Structural Vs. Functional.
Cadence’s Frank Schirrmeister questions whether advances in design and semiconductor technology have kept energy requirements to a reasonable level, in Towards Decarbonization: Keeping Electronics Energy Consumption In Check.
Synopsys’ Sam Tennent lays out how to meet competitive time to market requirements with virtual prototypes for early software development, in Eliminating Software Development Bottlenecks For SoCs.
Siemens EDA’s Rusty Stuber advises assessing code quality in each stage of development so initial project plans stay relevant longer, in Improving Predictability Through Design Solutions Methodologies.
White Papers
Raising The Bar With The Next Generation Of AI For Chip Design
Batch Filters: A Better, Faster Way To Filter Large DRC Results Databases.
Interop Shift Left: Using Pre-Silicon Simulation For Emerging Standards.
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