Top Stories

Challenges Grow For IP Reuse
Methodologies for integration become a competitive tool as complexity and possible options skyrocket.

Users Talk Back On Standards Process
How does a standard get created? A lot of hard work and balancing different opinions can be frustrating, but that communication is vital.

Carving Up Verification
Cadence’s verification chief discusses current best practices for dealing with design complexity.

Blogs

Editor in Chief Ed Sperling observes that it’s getting harder even for big chip companies to get designs out the door on time, in When Will It Be Done?

Technology Editor Brian Bailey contends that the standard for verification modeling has a misleading name, and it should be changed, in What Is Portable Stimulus?

Aldec’s Igor Gorokhov digs into FPGA-based use cases for reference designs, in Leveraging The Power Of VDMA Engines For Computer Vision Apps.

OneSpin Solution’s Dave Kelf finds that applying formal techniques to a classic logic puzzle results in plenty of creative solutions, in 10 Ways To Skin A Formal Puzzle.

Mentor Graphics’ Jeff Miller points to the need for a low-cost proof-of-concept, in IoT Edge Design Demands A New Approach.

ARM’s Nandan Nayampally examines how to boost performance with the same power envelope, in Ubiquitous AI.

ESD Alliance’s Bob Smith looks at trends, opportunities, danger signs, and the future of semiconductor design, in The CEO Outlook Returns.

Sponsor White Paper

Optimal Memory Strategies: Where HBM2 Fits
As functionality increases, so does memory content.