Top Stories
Adding NoCs To FPGA SoCs
As complexity and device sizes rise, so does the need for an on-chip network.
Searching For A System Abstraction
Hardware became stuck using the RTL abstraction, but system-level tasks need more views of hardware than are currently available.
Formal Abstraction And Coverage
What experts in formal verification are saying behind closed doors.
News
Wednesday At DAC 2018
What does the future look like and how are we going to get there? Many problems remain to be solved.
Blogs
Editor In Chief Ed Sperling observes that reliability is no longer about one chip, or even one device, in Toward Cross-Layer Resilience.
Technology Editor Brian Bailey questions whether engineers find comfort in details as they get older, and whether abstraction is for younger minds, in Abstraction Aging.
Mentor’s Ashish Hari, Aditya Vij and Ping Yeung show how the CDC intent of any block can be turned into a data model that can be seamlessly re-used across designs, in Raising The Bar On Flat CDC Verification With Hierarchical Data Models.
OneSpin’s Tom Anderson looks at why it took the industry so long to become comfortable with cloud-based tools, in The Skies Over EDA Are Finally Cloudy.
Aldec’s Farhad Fallahlalehzari shows how verifying the interaction between programmable logic and processing earlier in the design cycle pays benefits in time and cost, in SoC FPGAs And HW/SW Co-Simulation.
eSilicon’s Mike Gianfagna points to the benefits of utilizing IP that is relevant to a pre-specified chip architecture for boosting design productivity, in FinFET ASICs: It Takes A Platform.
Cadence’s Frank Schirrmeister zeroes in on the accuracy of predictions about interoperable models and designing in the cloud, in DAC 2018: System Design, Cloud And Machine Learning.
