FinFET ASICs: It Takes A Platform

Utilizing IP relevant to a pre-specified chip architecture to boost design productivity.

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Sophisticated, specialized ASIC technology is making an impact on the everyday world around us. Whether it’s a gadget you can have a conversation with, a car that will take over driving from time to time, or internet speeds that seem impossibly fast, there is likely sophisticated custom silicon present as a critical enabling technology. Plenty has been written about advanced ASICs for networking, computing, AI and 5G applications. FinFET technology is always part of the conversation. So is 2.5D packaging and the associated HBM2 memory stacks. We talk about high-speed interfaces and specialized memories.

All of this is really important and quite relevant, but there is another dimension that is often overlooked. In order to minimize time to market, you must avoid distractions from your one true mission – developing that core element of the chip that will make your product truly different. And in order to achieve that, you must make sure that you have all of the supporting elements not only available, but pre-integrated and pre-verified in such a way that they can be “plugged” into your design with predictable interoperability.

Consider that the elements of a typical advanced ASIC are delivered by more than one IP provider and several supply chain partners. How do you ensure all this capability works together? Even more daunting, how do you ensure you can configure parts of the design without breaking other parts? eSilicon has considered this problem for quite a while and our answer is clear.

You need a platform. A market-specific platform.

A platform delivers relevant IP to a pre-specified chip architecture. It ensures the IP is compatible across technology and operating condition choices and it delivers flexibility and configurability through careful design of the IP components. These tenets apply to the IP developed by the platform provider of course. But they also must apply to any third-party partner IP as well. Building a reliable and robust platform isn’t easy and doesn’t happen quickly.

The benefits of using a platform for FinFET ASIC design can be quite rewarding. For example: achieving the required performance for a switching ASIC by tuning memory configurations or adding a few SerDes lanes. Or, modifying the convolution algorithm for a deep learning ASIC by swapping one IP tile for another. The consistency, compatibility and predictability of a platform can be the margin of victory.

And yet, platforms do not serve every conceivable chip if you want to preserve the efficiency and performance that drove you to an ASIC in the first place. Platforms must be market-specific, even if many of their components are similar or the same. As an example, the PPA targets, number of elements and required bandwidth of an AI chip are widely different from a top-of-rack data center switching chip. So, one size does not fit all.

So, where does a platform fit then? If you build it properly and make it sufficiently configurable, it will be able to support many requirements across a given market. This works well for building families of products and derivatives.

Watch this space – there will be many platform announcements coming. For now, you can check out recent announcements from eSilicon regarding two market-specific platforms. Our 7nm neuASIC platform for machine learning and our 7nm platform for data center ASICs.



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