Special Report
Big Changes For Mainstream Chip Architectures
AI-enabled systems are being designed to process more data locally as device scaling benefits decline.
Top Stories
Gaps In Verification Metrics
Experts from Arm, Intel, Nvidia and AMD look at what’s missing from verification data and how to improve it.
Bugs That Kill
Behind closed doors: Semiconductor executives talk about the bugs they fear the most and the problems solving them.
Blogs
Editor in Chief Ed Sperling points to multiple levels of innovation plus AI in new chips, in Architects Firmly In Control.
Technology Editor Brian Bailey goes deep undercover to ask when removing someone from a project actually improves it, in Hiring And Firing.
Mentor’s Matthew Knowles contends that the process of test pattern bring-up, debug and device characterization is ripe for improvement, in Digital IC Bring-Up With A Bench-Top Environment.
OneSpin’s Sergio Marchese argues that engineers developing automotive chips need clear information, but some EDA vendors are muddying the waters, in Demystifying EDA Support For ISO 26262 Tool Qualification.
Cadence’s Frank Schirrmeister points to 5G devices, low power, system of systems, and architecture/performance as the key verification drivers, in Verification Trends Enabling A 5G Future.
Synopsys’ Bernadette Mortell observes that the complex process and layout rules for finFET processes have a big impact on decisions made during synthesis, in Is Synthesis Still Process-Independent?
Aldec’s Sunil Sahoo explains how to directly access registers by name from the testbench, without having to know where and what they are, in Accessing Registers With UVM-RAL.
Startup Corner
Carbon Nanotube DRAM
Is carbon nanotube memory too good to be true?
