Top Stories

Silo Busting In The Design Flow
Waterfall development flows no longer work for chip design, but unified tool flows may not be the answer.

Using AI And Bugs To Find Other Bugs
New methodologies are being developed to deal with increasing complexity.

Brute-Force Analysis Not Keeping Up With IC Complexity
How to ensure you’ve dealt with the most important issues within a design, because finding those spots is becoming a lot more important.

Blogs

Technology Editor Brian Bailey takes a look back over 2020 to see what everyone has been reading and which subjects are the most important to you, in What Interested You In 2020.

Cadence’s Frank Schirrmeister explains how new networking and architecture co-design opportunities are creating a fundamental shift in the data center, in System Design For Next-Generation Hyperscale Data Centers.

Codasip’s Roddy Urquhart describes the effect of adding RISC-V extensions to both core size and codesize, in Impact Of Instruction Memory On Processor PPA.

Mentor’s Abdellah Bakhali examines how to combine geometric and topological data for better reliability verification, in ESD P2P And CD Verification Doesn’t Have To Be Hard.

Synopsys’ Alan Courtay and Gobi Kengara Palayam Appavoo advocate using piecewise linear circuit models rather than models with full SPICE-level accuracy to perform earlier simulation, in Virtual Prototyping For Power Electronics Systems.