Special Report
Multi-Modal AI In EDA Development Flows
The development of a semiconductor system is more complex than just describing functionality in RTL. How ready are AI models to handle the larger task?
Top Stories
For Chip Developers, HW/SW Co-Design Key To Data Center Efficiency
Every aspect of data center energy use must be optimized to reduce power consumption and enable more sustainability, from chips to transformers and edge compute.
How AI Will Impact Chip Design And Designers
How AI is reshaping EDA, and how it will help chipmakers to focus on domain-specific solutions.
AI In Chip Design: Tight Control Required
Why and where limitations are needed in AI-driven design, and where software-defined hardware works best.
Video
Accelerating IP Reuse
How to put 1,000 pieces of IP into a chip design and make sure they work together.
Opinion
Hallucination And Innovation At DAC
What we can learn from hallucinations, and where AI will fit into the chip design flow.
Sponsor Blogs
Siemens’ Paul Carpine suggests it’s time to reassess the optimal temperature for electronics manufacturing facilities, in Baby, It’s Hot Outside!
Cadence’s Krunal Patel shows how link-layer retry can fix packet loss locally and avoid expensive recovery mechanisms, in UEC-LLR: The Future Of Loss Recovery In Ethernet For AI And HPC.
Arteris’ Insaf Meliane examines how a structured approach can ensure consistent IP metadata representation across abstraction levels, design tools, and development teams, in System Integration With Standards-Based Automation.
Keysight’s Richard Duvall looks at how new optimizer algorithms can impact increasingly complex chip designs, in What Is The Next Generation In RF Circuit Simulation And Optimization?
Synopsys’ Manoz Palaparthi explains why parallelized, hierarchical, and distributed timing analysis are necessary for HPC and AI chips, in STA Strategies For Fast And Efficient Signoff Performance For Multi-Billion Instance Designs.
Sponsor White Papers
Streamlining Functional Verification For Multi-Die And Chiplet Designs
Enabling full multi-die system functional verification and early testing long before interposer characteristics are pinned down, without requiring new test benches.
CodaCache Last-Level Cache IP
Standalone cache designed to enhance system performance, data locality, scalability, power efficiency, and cost-effectiveness in SoC designs.
Navigating The Quantum Revolution In A Year Of Transformation
Practical insights into the quantum landscape of 2025 and how organizations can benefit from this technological revolution.
Questa One Avery VIP: Accelerated Confidence In Complex Protocol Verification
Addressing complex interfaces and memory protocols for SoCs, 3D-ICs, chiplets, and FW/SW integration.
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