Special Report
Small Vs. Large Language Models
SLMs targeted at specific workloads could change the relationship between edge devices and the cloud, creating new opportunities for chipmakers, EDA companies, and IP vendors.
Top Stories
AI Plays Multiple Roles Within EDA
The application of AI into design tools and flows will take several forms, each independent, but all potentially working together.
FPGAs Find New Workloads In The High-Speed AI Era
Growing use cases include life science AI, reducing memory and I/O bottlenecks, data prepping, wireless networking, and as insurance for evolving protocols.
The Real-World Impact Of Silicon Lifecycle Management On Chip Architectures
Designing resilient chips with SLM can help combat aging effects, security threats, and get to market faster with higher yields.
Formal Verification’s Value Grows
But to increase adoption, formal tools have to lower barriers and make it possible for a wider group of people to be able to deploy successfully. LLMs may help.
The Future For Formal Verification
Will a formal specification be part of the future, or will we continue to see natural language specifications? Will formal successfully break out of just functional verification?
Video
Changes In Mixed-Signal IC Verification
Why digital and analog engineers must now find common ground.
Opinion
Spray And Pray Wastes Power
Given the importance of power to many chip designs, it is amazing how few tools take power seriously.
Sponsor Blogs
Baya Systems’ Nandan Nayampally explains why modern AI systems require dynamic, adaptable software layers built to handle changing computational needs, in Shaping The Future Of AI Processors: A Tech Threads Conversation With Jim Keller.
Siemens’ Sara Khalaf shows why automated IP checking matters, in Securing IP Integrity In Advanced SoC Design.
Arteris’ Tim Schneider digs into hardware/software interface consistency for RTL, drivers, verification, documentation, and firmware, in A Golden Source As The Single Source Of Truth In HSI.
Cadence’s Reela Samuel discusses bringing logic, memory, and accelerators into tight physical proximity, in What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts.
Sponsor White Papers
PCI Express Design Guide – Q&A for Gen 4, 5, 6
Part 1: 60 of the most common real-world design questions that engineers face—and provides detailed, practical answers grounded in simulation data, field experience, and compliance testing.
Faster Bug Discovery And Coverage Closure
Achieving efficient bug discovery and coverage closure is essential to prevent issues from reaching silicon.
IP And Data Management: Challenges, Solutions, And Best-in-Class Approaches
Results of an industry-wide survey of more than 900 professionals evaluating the state of IP and design data management.
From Bottleneck to Breakthrough: Scalable Fabric IP for High-Bandwidth AI and HPC Systems
Key architectural considerations that enable scalable, low-latency, and power-efficient data movement.
Guarantee IP Integrity With Calibre IP Checker
The value of comparing IP against original versions.
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