A Golden Source As The Single Source Of Truth In HSI

The hardware/software interface (HSI) is where system-on-chip (SoC) software defines the connections between the software and the underlying hardware. Maintaining a precise, synchronized HSI across all artifacts is challenging, and unmanaged deviations can propagate through the flow and affect integration schedules.

Most complex SoCs rely on IP reuse, each with its own naming conventions, hand-edited spreadsheets, wikis, and scripts that can fragment and drift quickly. This could create a disconnect between the software’s view of the device and what the silicon implements. Teams must also manage bug fixes and evolving standards. To mitigate risk, Arteris technology automates generation from a golden source input, keeping the HSI consistent across RTL, drivers, verification, documentation, and firmware.

From source to system

Arteris products provide a solution by capturing the HSI in a machine-readable format and updating all dependent artifacts on every build. Using Magillem Connectivity and Magillem Registers, teams package IP, compose system maps, elaborate registers, and produce synchronized outputs, including netlists, UVM RAL, C headers, and HTML documentation, all from the same description. Generators and checkers operate together to catch connectivity errors and conflicts early in the process.

By generating all outputs from a single source and automatically validating them, Arteris builds consistency into the process. IP is packaged with interface metadata, parameters, clocks/resets, and legal settings. Hierarchical address maps contain other address maps. Leaf maps contain registers and memories. Because Magillem supports IP-XACT and SystemRDL/CSRSpec, the same description can instantiate components, elaborate the address space, and emit synchronized views for all stakeholders.

A typical flow includes:

• Importing and packaging IP, loading AMBA definitions, and mapping physical ports to logical bus interfaces.
• Merging memory maps, composing the top level, and instantiating and configuring components.
• Connecting bus interfaces and ad-hoc signals, then validating the structure with protocol and connectivity checks.
• Restructuring hierarchy to meet PPA goals while maintaining logical intent.
• Creating all downstream outputs from the unified source.

Since all outputs originate from a unified design model, protocol and width rules such as AXI, APB, word sizes, alignment, and byte-enables are applied consistently.

Fig. 1: Magillem Platform from Arteris solves SoC integration challenges. (Source: Arteris)

Proof points

To demonstrate the flow:

Arteris integrated PULPino, an open-source single-core 32-bit RISC-V microcontroller SoC, with an AXI4 core/data/instruction path, APB peripherals, and a dual FlexNoC interconnect fabric into a dual-core system. From the unified source, the team exported a UVM Register Abstraction Layer along with matching HTML register documentation. The UVM testbench ran access, reset, and mirror/predict checks to guarantee alignment between RTL and the software-visible view.

Measured results show:

A 3x increase in speed generation, 5x the design capacity in register management, and a 35 percent reduction in HSI development time, with lower late-stage risk achieved by eliminating duplicated sources of information.

“The product doesn’t ship unless the device drivers work!” This phrase captures the interdependence between software and silicon realities that this methodology helps resolve. This connection between software and hardware makes early coordination and automation essential.

Effective HSI practices emerge naturally when a single, machine-readable golden source drives the design flow.

1. Bring software in early. Keep driver authors aligned with RTL using generated headers and documents.
2. Separate hierarchical and leaf maps. Compose maps apart from leaf registers/memories.
3. Decide top-level word size early. Standardize the developed maps to a common width.
4. Be cautious with byte-enables. Pick a system-wide stance to avoid verification and software friction.
5. Treat fields as the atom. Modeling at the field level yields better UVM and cleaner header creation.
6. Avoid mixed-access registers. Separate unrelated behaviors into distinct registers.
7. Don’t smash your system map. Leave headroom and cluster related functions for simpler decoders.
8. Automate validation. Run protocol and connectivity checkers and regenerate outputs on every build.

Fig. 2: PULPino SoC integration example. (Source: Arteris)

Keeping hardware and software aligned

Arteris Magillem Registers produces a UVM RAL model based on the input description in CSRSpec, SystemRDL, or IP-XACT, encoding register behavior such as access types, reset checks, and mirror or predict operations. Because the UVM model, RTL, and C headers are created from the same input, backdoor paths and prediction logic remain consistent even when RTL hierarchy changes for floorplanning. The same source also produces HTML documentation, keeping field names, bit positions, and access rules aligned across hardware and software views.

Magillem Connectivity automates interface mapping and validation, producing reports that flag protocol incompatibilities and mismatched interfaces before RTL generation. Because interface and architecture intent are captured in the IP-XACT description, hierarchy restructuring can be done safely without breaking logical intent.

The single source of truth also makes changes traceable. Updates to fields, reset values, or access types can be compared and merged across versions, with continuous integration (CI) flows detecting mismatches automatically.

The heart of reliable system design is trust between hardware, software, and the teams that build them. When structure replaces guesswork and automation enforces intent, integration stops being an act of faith and becomes a verifiable process. In that alignment, every register, every driver, and every line of code works toward the same outcome, where hardware and software meet exactly where they should.

Together, Magillem Connectivity and Magillem Registers form the foundation of the Magillem Platform, the environment that drives Arteris’ automation for SoC integration and verification.