Top Stories

Which IP Is Better? – Just because the specs look better doesn’t mean one piece of IP will actually work better than another when it’s integrated into a complex chip. A number of strategies have emerged for picking the right IP—hopefully.

How Close Is Close Enough? – Computers are being developed capable of approximate computing, where 100% accuracy isn’t required, but how well does that concept map to power management?

Performance Still Trumps Power – Despite all the claims about power becoming the dominant design consideration, it still hasn’t achieved that distinction. In most designs, performance still comes first. Here’s why.

Power’s Impact On Hierarchy Modification – RTL restructuring to manage complex designs has become commonplace, but what happens when power management is added into the mix?

The Road Ahead For 2014 – Identifying market trends is the first step in being able to ensure you have the right products when people need them. Here’s what the industry’s thought leaders see coming.

Blogs

Editor’s Note
Setting energy policy should be a national priority, but it appears to be more of a localized lobbying effort with no cohesive goals. A look at what’s gone awry in Power Vs. Policy.

Power Aware A-Z
Mentor Graphics’ Christen Decoin looks at why effective power grid analysis will be critical to designs in Power Grid Analysis—Challenges At 20nm And Below.

Everything Low Power
Cadence’s Brian Fuller identifies Three Must-Watch Electronics Trends in 2014.

IP And LP In SoCs
Synopsys’ Matthew Myers looks at how to add flexibility and backward compatibility to standard I/O Using USB 3.1’s Multiple INs To Reach 10 Gbps Data Rates.

Power Architect
Nvidia’s Barry Pangrle unearths a promising new trend involving delay insensitivity, which is moving from drawing board to real circuits in Making Waves In Low-Power Design.

Power Awareness
Is it possible to manage power in SoC designs simply? Maybe, but as Ann Steffora Mutschler points out, Simple Does Not Mean Easy.

The Early Edition
Atrenta’s Mark Baker argues that design tools aren’t doing their job in finding power reduction opportunities in Power Resolutions For 2014.

Power Source
ANSYS-Apache’s Aveek Sarkar digs into changing requirements for design teams in Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era.

Power Down
Calypto’s Rob Eccles compares sequential to combinatorial optimization in Verifying Power Optimized Designs Using Sequential Analysis.