Which IP Is Better?

As the amount of third-party and re-used IP in a semiconductor increases, so do the number of questions about which possible IP choices perform better, use the least power, or work best with other components. So far, there is no simple way to make that choice.

In most cases, this is simply splitting hairs. For all the IP that goes into designs, the bulk of it is chosen based on how often has it been used in silicon, whether it readily available, and how much it costs. But IP also is a differentiator for many companies, and IP can make the difference in certain applications and markets.

“One area where we see issues is when the implied timing is not what external components expect,” said Ty Garibay, vice president of IC engineering at Altera. “The soft IP guys don’t tell you and the external guys don’t know what it is. If there was a way to standardize that, it would be good. But board design is still something of a black art. You can’t simulate all possible combinations, and the customer still expects it to work.”

A common approach to dealing with this problem has been detailed characterization of IP. In theory, that should make it easier to pick and choose IP from a variety of vendors based upon configuration, price, performance specs and power envelope. Reality is somewhat different, however, which has led to four main approaches for choosing the best IP for a design.

1. Testing one, two…11, 12…
For those companies that can afford the time to test out various IP offerings, running side-by-side comparisons is the method of choice—particularly in a real design or prototype of that design.

Step No. 1 is to figure out exactly what the IP needs to do. This may sound obvious enough, but it’s easier said than done—particularly in complex design where there are multiple power domains, processors, memories and various states and modes.

“If you’re working with an ARM fabric, it’s probably already integrated,” said Jason Polychronopoulos, verification IP product marketing manager at Mentor Graphics. “Beyond that, each stage is more effort. You plug it in, try it out, and run an experiment or evaluation. So maybe you start with 10 possibilities and narrow it down to one. And you do a certain amount of risk assessment with that. If it’s well-known and proven, that’s pretty quick. If it’s a new protocol IP, that requires more work on your side. And then, once you get it plugged in, there are multiple ways to make it better.”

One of those ways is incoming quality inspection. While functional correctness is based on references and prior usage, there are other components such as timing exceptions that have a history of problems in IP, according to Bernard Murphy, chief technology officer at Atrenta.

“Some of the best groups and companies are now asking for qualification tests before acceptance,” Murphy said. “This started in the verification domain, but is also moving to design. Power is particularly challenging since implementation and usage can dramatically affect actual power. The only way to get this right is to ensure advertised power is in the ballpark, then expect to work with the supplier to fix any problems arising from your usage.”

2. Getting extra help
Making IP work better isn’t so simple, though, even with commonly used IP such as PCIe or USB 3.0. For one thing, large chipmakers have shifted their emphasis from hardware IP to software, leaving gaps in their in-house expertise.

“The real problem is power management, how you mesh IP information, testability and clock-domain crossing,” said John Koeter, vice president of marketing for Synopsys’ Solutions Group. “As customers move upstream, they’re requiring more and more services. The hard part is not finding the IP. The hard part is integrating it into the overall IC. This is less about the process node and more about where the customer is at. What we’re finding is that as customers outsource more IP, they’re losing that internal knowledge.”

He noted that the biggest demand for those services is in North America, followed by Europe and Japan. “Those are the people working on complex SoCs,” Koeter said. “They have more of their budget committed to software, and they backfill through IP.” There is far less demand for those kinds of services in developing markets such as China, which may sound counterintuitive given the fact that IP is supposed to be the fastest way of assembling an SoC.

Cadence’s approach is less expert-intensive, putting more configurability into the IP and less emphasis on the professional services. “There is a medium between professional services and the jelly bean, off-the-counter IP,” said Susan Peterson, group director for VIP marketing at Cadence. “We call this an IP factory, where you are able to increase the level of customization on more mature technology nodes. That’s a lot different than a brand new protocol on new process technology where you have less leeway.”

Peterson noted that the key is IP and tools in context, not in isolation—and there may be hundreds or even thousands of possible configurations to optimize the IP.

3. Reuse
Another common strategy is re-using the same IP in new designs. While that frequently works well using the same process or even derivatives in different process technologies, it’s not foolproof.

“One of the biggest challenges is when you have IP tuned and targeted for a particular spec and technology and frequency, and then you move it to a new generation of designs and new technology,” said Shawn McCloud, vice president of marketing at Calypto. “The first problem is that you may have a microarchitecture with concurrency or parallelism in the design and the logic between the register boundaries is all locked down. Proven IP is the most important in terms of time to market, but you may give up silicon and performance. If one company comes out with IP that is better tuned, it could be a competitive advantage for them. You see that with Apple, which took charge of its own IP and it came out with the lowest power microprocessor on the market.”

On the digital side, much of the complexity is absorbed by network on chip technology or ARM’s AMBA bus, where variations are handled by the fabric. Analog is a whole different story.

There are two distinct sides to analog IP. One involves fairly standardized PHYs, and most companies use what’s available from IP vendors for that. When it comes to advanced PHYs and other high-performance analog—particularly at the leading edge of process design—most companies still opt to develop the IP themselves or work closely with a specialized provider.

“For very high speed analog, we spend a lot of time developing it and we have very few unanticipated problems,” said Altera’s Garibay. “But the other stuff you just expect to work.”

4. Rolling your own
At the leading edge of process technology, buying commercial IP frequently isn’t a possibility. The volume of commercially available IP for 16/14nm, for example, is a small fraction of what’s available for 28nm.

“Internal IP is typically much messier, especially where there is no disciplined re-use strategy,” said Atrenta’s Murphy. “In practice, known-good IPs are proven only in a very limited set of contexts and have never been ‘hardened’ for broad and varied usage. Because the original designer is often no longer available, a new application of an IP to a more demanding spec frequently allows time only for cosmetic changes, some quick tests and fervent hope that you didn’t overlook some subtle boundary condition.”

At the same time, some of that IP is custom-made for a design, particularly on the analog side. That means, at least for that one design, it should work.

“With digital IP, you try to get an absolute top clock speed, or at least an understanding that it runs in a range that’s well proven,” said Derek Meyer, an Andes Technology consultant. “But with mixed signal, you can’t change it so it has to work. The variance is less because it’s a custom design and you know the results. If the requirement demands custom development and you’re not going to do it yourself, it’s important to pick a supplier with a good track record. On the digital side, there is more data and more variability, and which vendor’s tool flow you’re using and which library you’re using all can affect the final result.”

He noted that the best solution with digital IP, particularly for critical functions, is to try it out. “You wouldn’t buy a car without test driving it,” Meyer said. “The big issue there is the integration of a variety of IPs. There’s an incorrect assumption that if everyone buys commercial IP then all SoCs will look the same. That’s absolutely not true. Integration of IP is where the differentiation comes in, and the more data you get earlier in the design cycle the more likely you are to achieve better results.”