tag: Calypto Design Systems

Making Chips Run Faster
By Ed Sperling - 11 Sep, 2014 - Comments: 3

For all the talk about low power, the real focus of most chipmakers is still performance. The reality is that OEMs might be willing to sacrifice increasing performance for longer battery life, but they will rarely lower performance to reach that goal. This is more obvious for some applications than others. A machine monitor probably isn’t the place where performance will make much of a dif... » read more

Low Power Design: RTL Power Analysis
By Anand Iyer - 11 Sep, 2014 - Comments: 0

In last month’s blog, we discussed and compared various power techniques. A quick recap of these power techniques is shown in figure 1. Selecting between them is often quite challenging. These techniques need to be selected during RTL design. At the RTL, designers need a power analysis solution that guides them to the right techniques for their design. In this month’s blog, we will review t... » read more

Architecting For Efficiency
By Ann Mutschler - 10 Apr, 2014 - Comments: 0

By definition, to be efficient is to perform or function in the best possible manner with the least waste of time and effort; having and using requisite knowledge, skill, and industry. As this relates to SoC design today, achieving the highest level of efficiency is a challenge with many dimensions. Efficiency comes in multiple ways. “One dimension would be power consumption,” said Oz Le... » read more

Which IP Is Better?
By Ed Sperling - 16 Jan, 2014 - Comments: 0

As the amount of third-party and re-used IP in a semiconductor increases, so do the number of questions about which possible IP choices perform better, use the least power, or work best with other components. So far, there is no simple way to make that choice. In most cases, this is simply splitting hairs. For all the IP that goes into designs, the bulk of it is chosen based on how often has... » read more

The Path To Power Signoff Is Getting Longer
By Ed Sperling - 06 Dec, 2013 - Comments: 0

Signoff on power used to be a fairly simple check-the-box kind of activity. Even if power budgets weren’t exactly met, they could usually be fixed in future iterations of a chip, whether that involved derivatives or new revs of the same chip. A number of things have changed since the much simpler days of 45/40nm and above, however. Power is now a market differentiator. In many cases, i... » read more

Will History Repeat Itself?
By Brian Bailey - 24 Oct, 2013 - Comments: 0

Hands up — how many people read the books by Clayton Christensen, books such as The Innovator’s Dilemma? His books were talked about endlessly in the corridors of the EDA companies when they first came out. They all wanted to identify the next disruption and could find reasons why almost every new tool was going to be disruptive. For people not familiar with his work, his main premise wa... » read more

Experts Panel And Tutorial At DVCon
By Graham Bell - 31 Jan, 2013 - Comments: 0

Besides our usual exhibit at the Design and Verification Conference in Santa Clara at the end of next month, Real Intent has organized a panel and a half-day tutorial that highlights some of the changes happening in our industry—and which may have been overlooked. The panel addresses the interesting topic “Where Does Design End and Verification Begin?” The abstract states that design a... » read more

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