Experts Panel And Tutorial At DVCon

What’s changing in the IC design industry—and what may have been overlooked.


Besides our usual exhibit at the Design and Verification Conference in Santa Clara at the end of next month, Real Intent has organized a panel and a half-day tutorial that highlights some of the changes happening in our industry—and which may have been overlooked.

The panel addresses the interesting topic “Where Does Design End and Verification Begin?” The abstract states that design and verification are “joined at the hip,” as the initial spec for simulation and architectural exploration leads to an RTL model and finally a gate-level implementation. It claims that the verification flow applies assertions, testbenches, timing constraints and automation methods as the design devolves. Are they completely entwined? From what I have seen, design teams typically see a boundary between those who write the RTL code and those who verify it. Is there a clean hand-off between D and V? And what is the best practice for the industry? I look forward to hearing what the moderator, Brian Hunter of Cavium Networks and the panelists—John Goodenough (ARM), Oren Katzir (Intel), Harry Foster (Mentor), Pranav Ashar (Real Intent) and Gary Smith (GSEDA)—will say about these questions on the morning of Wednesday, Feb. 27.

Secondly, the half-day tutorial on “Pre-Simulation Verification for RTL Sign-off” presents the toolset that surrounds the traditional dynamic simulation and timing analysis used by engineers. The integration of heterogeneous IP and design units into an SoC requires confirmation of protocols, power budgets, testability and the correct operation of multiple interfaces and clock domain crossings (CDC). Simulation theoretically can be used to fully test an SoC, but the cost of complete RTL testing is beyond what design teams can afford. To reduce cost and the risk of missing critical tests, abstract modeling and pre-simulation static analysis of RTL have become imperative in SoC design flows.

The presentations will cover power exploration, analysis and optimization using an abstract model with high-level synthesis (HLS), followed by the RTL static verification for: syntax and semantic checking (lint); constraints planning and management; reset analysis and optimization; automatic intent verification; CDC signoff; DFT analysis and insertion; and X-analysis and optimism/pessimism correction. Each step represents a substantial hardening of the design and is best served by a top-of-the-line tool designed specifically for that step.

The following elements will be presented:

  • Power estimation and optimization of a hardware subsystem using HLS;
  • Latest lint checks including loop detection, FSM, low-power, and mixed-language issues;
  • SDC correctness and consistency versus RTL changes from power and clock-gating optimizations;
  • Reset flop analysis and later optimizations to reduce the number of required flops;
  • Automatic formal analysis to verify design intent;
  • CDC sign-off flow using formal and structural methods;
  • Testability sign-off, DFT verification and planning, and proper DFT implementation, and
  • Correct X-hygiene in preparation for simulation.

The three-hour tutorial on the afternoon of Thursday. Feb. 28, will include presentations from experts at Calypto Design Systems, DeFacTo Technologies, and Real Intent:

Bryan Bowyer, Sr. Design Specialist, Calypto Design Systems
Bryan Bowyer is a leading expert in designing with high-level synthesis (HLS), with more than 12 years experience both designing and using HLS tools. Bryan has created a wide range of hardware using HLS, from FFTs to AXI Interfaces in C++ and SystemC. Bryan currently is leading the product pesign team at Calypto Design Systems, and is responsible for HLS, formal equivalence and power optimization.

Chouki Aktouf, President and CEO, DeFacTo Technologies
Prior to founding DeFacTo, Dr. Aktouf was an associate professor of computer science at the University of Grenoble 2 and leader of the dependability research group within the INPG (Institut National Polytechnique de Grenoble), where more than 18 man-years of work were applied to what is now DeFacTo’s unique approach to design for test (DFT). He holds a PhD in Electric Engineering from INPG (France) and did post-doctoral research in the electrical engineering department at University of Southern California in Los Angeles and Dalhousie University in Canada. A member of the IEEE and TTTC, Dr. Aktouf has more than 15 years experience in design and test and in fault-tolerance. As well as leading several international research projects in the USA (DARPA), Canada (NSERC) and Europe, he has published more than 150 scientific publications in international conferences, periodicals, magazines and several book chapters.

Pranav Ashar, CTO, Real Intent
Dr. Pranav Ashar brings two decades of EDA expertise to Real Intent. Dr. Ashar received his M.S. and Ph.D. in EECS with emphasis on EDA from the University of California at Berkeley in 1989 and 1991, respectively. He then joined NEC Labs in Princeton, N.J., where he developed a number of EDA technologies that have influenced the industry. He has authored about 70 publications in refereed conferences and journals with approximately 800 citations, and co-authored a book titled “Sequential Logic Synthesis.” He has 35 patents granted and pending, many of which have been licensed or part of business enablement. Dr. Ashar was an adjunct faculty in the CSEE department at Columbia University, where he has taught graduate and undergraduate courses on VLSI design automation, VLSI Verification, and VLSI design.

The cost for the tutorial is $85 unless you choose one of the conference registration packages that include the tutorial.

I look forward to hearing back from the SLD readership on what they thought of the panel and the half-day Tutorial. See you at the show!