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Week In Review: Design, Low Power


IP, FPGA, Tools Arm released new details on its new Neoverse N2 and Neoverse V1 platforms. A range of companies announced they will be using the platforms, including Marvell and SiPearl. Aimed at server and HPC workloads, Neoverse V1 uses wider and deeper pipelines compared to the N1 and supports a 2x256bit wide vector unit executing the Scalable Vector Extension (SVE) instructions with sup... » read more

Experts Panel And Tutorial At DVCon


Besides our usual exhibit at the Design and Verification Conference in Santa Clara at the end of next month, Real Intent has organized a panel and a half-day tutorial that highlights some of the changes happening in our industry—and which may have been overlooked. The panel addresses the interesting topic “Where Does Design End and Verification Begin?” The abstract states that design a... » read more