Anand Iyer

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Anand Iyer is director of marketing for the low power platform at Calypto.

Author's Latest Posts

A Strategy For Designing For Power With FinFETs
By Anand Iyer - 11 Sep, 2015 - Comments: 0

Recently Qualcomm announced their new SnapDragon processor 820, which was designed using finFET technology. They showed some amazing results, such as 2X improvement in performance and 2X improvement in power compared to 28nm designs. Previously, when ARM announced their A72 processors in finFET, they too had claimed 3.5X improvement in power compared to 28nm designs. But can designers expect... » read more

Doing More With RTL Power Analysis: Smart Synthesis Architecture
By Anand Iyer - 13 Aug, 2015 - Comments: 0

Traditionally RTL power analysis has been used to understand the design power consumption so that package and power supply designs can start, and designers can then fix any power regression violations in subsequent design iterations. However, migration to finFET processes is causing designers to look at RTL power analysis differently at advanced nodes. FinFET processes have largely addressed... » read more

Microarchitecture Design For Low Power
By Anand Iyer - 14 May, 2015 - Comments: 0

As designs move to finFET process nodes, dynamic power reduction has become a requirement. Designers have to eliminate or minimize all sources of redundant switching activity in order to reduce dynamic power in the design. In our last blog, we looked at dynamic power wastage due to redundant adders and multipliers and how to gate these operators to save power. We also mentioned a couple of m... » read more

Low Power Paradox
By Anand Iyer - 13 Mar, 2015 - Comments: 0

Power has been an important design challenge for quite some time. Leakage power started to grow in 90nm, and by 65nm it became a severe design issue. We have built many techniques to address leakage, most notably power gating. These techniques are complex and have an impact on the design as a whole. FinFET technologies are seen as a boon to this issue of leakage. There are references that qu... » read more

(Low) Power Predictions 2015
By Anand Iyer - 15 Jan, 2015 - Comments: 1

Happy New Year! As we step into the New Year, lots of exciting things are already underway. First of all, the Internet of Things (IoT) is shaping up in a big way as witnessed at CES last week. Advances in devices that can talk to each other and share information are becoming a reality. Automotive applications, medical devices, industry automation, energy distribution and entertainment are all a... » read more

Low Power Design: RTL Power Analysis
By Anand Iyer - 11 Sep, 2014 - Comments: 0

In last month’s blog, we discussed and compared various power techniques. A quick recap of these power techniques is shown in figure 1. Selecting between them is often quite challenging. These techniques need to be selected during RTL design. At the RTL, designers need a power analysis solution that guides them to the right techniques for their design. In this month’s blog, we will review t... » read more

LP SoC Design: Part 2
By Anand Iyer - 16 Jul, 2014 - Comments: 0

In my last blog I talked about why designers need to rethink their methodology for low-power design and also introduced gross and fine-grain low power techniques. In this blog I am going to compare and contrast these techniques. Low-power design techniques fall under two categories, gross and fine-grain. Gross techniques are not dependent on the design or the process. Techniques such as powe... » read more

Low-Power SoC Design
By Anand Iyer - 08 May, 2014 - Comments: 1

Over the last decade, power has become the primary design constraint for all SoC designs. While power reduction started in mobile market segments due to the battery considerations, it quickly has become equally important to powerline applications due to the cooling costs. Today, CPUs define a power constraint called Thermal Design Power (TDP) for the market it operates. One of the definition... » read more

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