LP SoC Design: Part 2

In my last blog I talked about why designers need to rethink their methodology for low-power design and also introduced gross and fine-grain low power techniques. In this blog I am going to compare and contrast these techniques.

Low-power design techniques fall under two categories, gross and fine-grain. Gross techniques are not dependent on the design or the process. Techniques such as power gating, and dynamic voltage and frequency scaling, fall under this category. These techniques are useful but also can hide real design issues that cause extraneous power consumption in the first place. For example, a poorly architected design may use a number of low Vt cells to meet timing requirements. However, designers may find the resulting leakage to be excessive and may decide to implement power gating to meet the leakage requirement. In other words, power gating may hide a poor architecture in order to meet all the specifications.

These techniques are suitable for complex legacy designs or when the design team does not have a lot of time to tune their design. Implementing them is not trivial and requires substantial design and schedule commitment. Automation is available to make these techniques relatively error-free, with a number of low power checkers and a standardized format for specifying the power intent. These techniques have a concept of power domains where one set of rules applies. The power intent formats, such as UPF and CPF, are used to describe these rules for a particular design. The implementation tools attempt to obey these rules, and checking tools are used to catch any violations. The following example (Figure 1) shows a snippet of a rule for power gating and how implementation and checking tools behave.

Figure 1: Power gating rule

Fine-grain techniques are highly design-dependent. These techniques can be further divided into design and process categories. The fine-grain design techniques analyze the design for power saving opportunities, while fine-grain process techniques utilize processing capabilities to come up with power savings opportunities.

Examples of fine-grain design techniques are clock gating, memory gating, and data gating. These techniques require rigorous design analysis to assess and implement power savings opportunities. Analysis of the design exposes redundancies in computation that can be eliminated to optimize for power. For example, if a variable is written over and over with the same value, it can be optimized so the value is written once with the remaining writes gated off to save power.

Examples of fine-grain process techniques are multi-Vth, low-power process, and back biasing. These techniques utilize process technology features to save power. These techniques also require design analysis and can be applied to specific portions of the design. For example, multiple threshold voltage transistors can be used selectively based on the timing criticality of a specific path.

Figure 2 summarizes the different power techniques that can be used for saving power in a design.

Figure 2: Low power techniques summary

In my next blog I will talk about when to apply these techniques and what the tradeoffs are between these techniques.