Low-Power SoC Design

The current methodology needs rethinking to address gross and fine-grain techniques and the best low-power logic structure.


Over the last decade, power has become the primary design constraint for all SoC designs. While power reduction started in mobile market segments due to the battery considerations, it quickly has become equally important to powerline applications due to the cooling costs.

Today, CPUs define a power constraint called Thermal Design Power (TDP) for the market it operates. One of the definitions of TDP is that it is the maximum power allowed without causing a thermal runaway. It is also termed “realistic” worst-case power. The equation for TDP can be given as:

TDP = Vcc*(DIcc+SIcc) where, Vcc – voltage, DIcc – Dynamic current and SIcc – Leakage current.

Why is TDP important? Because it gives the range for the chip operation in real-world conditions. It also sets up standards under which companies can differentiate on known metrics such as features and speed. Today, we can evaluate a part on its TDP for a given market segment. For example, today’s mobile market TDP is ~1W. Any part over 1W will not make it to this market. It is also interesting to see how TDP has changed over time. The following chart illustrates the TDP changes for CPUs for three markets (desktop, laptop and mobile) over time . The numbers are normalized to 1GHz operation frequency as an illustration.

Figure 1:  TDP chart for CPUs

Figure 1: TDP chart for CPUs

Looking at this chart, we can see that the TDP itself has dropped dramatically over the last 15 years, keeping up with Moore’s law. For example, the TDP of laptop market has shrunk from nearly 45W in 1999 to 10W now. In 1999, the chip was running at 266MHz and now it can run at 1.7GHz. Another key point is that the TDP gap between adjacent market segments also has shrunk. For example, the gap between desktop and laptop used to be 35W and now only 20W.

Now let us look at how the process technology is keeping up with power. Figure below is the ITRS 2012 SoC power consumption trend chart.

Screen Shot 2014-05-06 at 8.13.25 PM

If you put figure 1 and 2 together, the result is a huge gap between the power requirements warranted by the market and the actual power of the SoCs. This gap is growing with newer designs in advanced process nodes. We need to rethink current power methodology if it is adequate to address the growing power challenges.

Existing methodologies use two distinct methods for reducing power– (1) Techniques that use changes to the existing logic structure to save power (e.g., clock gating, multi-vt, area reduction) and (2) Techniques that use the gross system behavior to save power (e.g., power gating, DVFS, voltage scaling). Keeping the RTL structure fixed and keeping these techniques separate, designers are left with inefficient RTL structure and increasing schedule time for their designs.

We need new methodology to address both the above issues. First of all, the tools must be cognizant of how the gross and fine-grain techniques interact and which combination of techniques is best for the design. Secondly, the methodology should guide designers to choose the best low power logic structure for their designs. This requires close interaction of exploration, analysis, optimization and verification steps.



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