Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era

As designs trend to sub-20nm FinFET process nodes, the focus on power noise and reliability sign-off becomes a necessary requirement. Adoption of new simulation solutions will help ensure greater confidence in sign-off accuracy and coverage.

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There is a greater focus on power noise and reliability simulations and sign-off as the complexity of SoC designs continue to increase with 100+ different voltage islands, clock and power gating techniques, and multiple IPs each operating on different clock and power domains, etc. The technology node migration from 40nm to 20nm is driving requirements for electro-migration (EM) and reliability sign-off and the increased competitive and business pressures are necessitating more attention to chip-package-system co-design and optimization.

Furthermore, the impact of power noise and reliability for SoC designs is going to become significantly worse as they migrate to FinFET-based processes. Based on the data from foundries and other sources, the use of FinFETs not only introduces additional challenges but also increase existing ones, especially with voltage drop, EM and overall power noise reliability sign-off needs. FinFET devices offer significantly higher drive strengths, resulting in sharper current transients, creating more localized di/dt current scenarios. Adding this to more resistive and inductive chip-package power grid networks can result in higher levels of dynamic voltage drop or transient noise.

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Figure 1: Benefits of FinFET in reduced operating voltages from figure of merit circuit delay vs supply voltage study (Source: Rob Aitken, ARM, Internet source)

The use of FinFETs enable design teams to operate their chips at significantly lower supply voltages. This has an immediate benefit in reducing their dynamic power consumption without impacting their standby currents (Figure 1). However, lower supply voltage also means smaller noise margin. For example, 200mV noise at the sub-700mV supply levels can be fatal for the chip’s performance and functionality. In addition, on-chip decoupling capacitors are becoming increasingly ineffective in ensuring local charge availability for fast charging devices.

With higher voltage drop noise and reduced noise margins, it is important to accurately predict the chip’s dynamic voltage drop. This requires accurate modeling and incorporation of all the different elements that interplay during any switching event on the chip, such as the transistors, the on-die diffusion, interconnect and gate capacitances that influence the charge transfer sources, and the parasitics (RLCK) from the on-chip/package/PCB interconnects that can impede the current flow.

Performing sign-off quality SoC dynamic voltage drop analysis requires accurate prediction of current flow inside the package, through the bumps and inside the chip (both at the higher and local metal layers). As these elements are tightly coupled, accurate sign-off cannot be achieved by simulating each block individually or by using divide-and-conquer or hierarchical modeling methods. Hierarchical techniques have limited ability to model time varying current flow across block boundaries, and in the on-chip/package power and ground interconnects. These currents vary based on the supply voltage seen at every device at every instant of time, the capacitances that are present in the network, and is modulated by the interconnect impedances. Pre-defined current profiles from hierarchical models neither adapt to these requirements nor do they reflect the actual operation of the chip.

Running ‘flat’ simulations that include the chip’s operation along with the package/PCB parasitics can predict the coupling across the chip, among the various blocks and domains, and into the package. But given the trend for increasing design size, ‘flat’ simulation techniques have to smartly handle the modeling complexities and look at distributing the design database across a network of machines by carefully balancing the accuracy and performance trade-offs.

For increased sign-off confidence, designers need to run multi-mode, multi-scenario analyses, as well as select appropriate vectors to drive the chips’ activity. Since gate-level vectors are scarce, RTL vectors that are carefully selected based on RTL power analysis should be used to drive the design activity. Often times, statistical or vectorless methods are used to predict the switching scenarios. Additionally, tying the results of the dynamic voltage drop analysis on the actual timing and operation of the chip, especially for the clock network and critical paths provides more comprehensive design coverage.

The design of chips’ package and the board can impact its performance and long-term success. The inclusion of package/PCB interconnect models for the chip dynamic voltage drop analysis has become de-facto requirement. But the quality of the model does not depend solely on the accuracy of the parasitic elements. It needs to be fully distributed in its connection to the chip and provide accurate parasitic elements for all interconnects versus treating any one net or bump as a virtual reference. The SoC design team should be able to visualize and assess the impact of the current flow in the package traces to make necessary adjustments and fixes.
EM and ESD are becoming limiting factors for sub-20nm designs. As seen from foundry data, the EM limits for vias are generally 70% of what they were for prior technologies while the current levels are 25 to 30% higher. In FinFET-based technologies the locally generated heat from the fins worsens the thermal signature of the chip, which further exacerbates the EM and ESD problems. A common practice among leading edge CPU and application processors designs is to include chip-package thermal analysis as part of the simulation methodology, using the chip thermal profiles to re-assess the EM and ESD signatures on the chips.

Adding traditional ESD protection devices is not possible in FinFET technology, so there is a shift to using larger and less effective diodes. To prevent ESD induced failures, the designers need to carefully design, select the placement and analyze the connectivity of these devices. Traditional approaches of using ‘design guidelines’ or ‘plot checks’ are too limiting and error prone. Layout based simulation techniques that consider the parasitics of the on-chip interconnects, incorporate their connectivity to the ESD protection devices and predict the flow of current in these wires during an ESD event are required to identify, isolate and fix any possible failure scenarios.

As designs trend sub-20nm FinFET process nodes, the focus on power noise and reliability sign-off becomes a necessary requirement. Simulation solutions that have the capacity and modeling sophistication to enable ‘flat’ analysis while considering various on-chip and chip-package coupling mechanisms, as well as power noise impact on reliability such as EM and ESD, will ensure greater confidence in sign-off accuracy and coverage.