Top Stories

Using Less Power At The Same Node
When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.

Memory Tradeoffs Intensify In AI, Automotive Applications
Why choosing memories and architecting them into systems is becoming much more difficult.

Using Analog For AI
Can mixed-signal architectures boost artificial intelligence performance using less power?

Videos

2.5D, 3D Power Integrity
Things to consider in advanced packaging.

Blogs

Editor In Chief Ed Sperling contends that tolerances are going to be very tight at the next nodes, where research is just beginning, in Power Budgets At 3nm And Beyond.

Rambus’ Frank Ferro explains how PCB materials and vias can address insertion loss and crosstalk, in GDDR6: Signal Integrity Challenges For Automotive Systems.

Cadence’s Rohit Kapur shows the different DFT technologies and when to insert them into a design, in IC Test: Doing It At The Right Place At The Right Time.

Mentor’s Harry Foster questions whether verification techniques are keeping up with FPGAs’ growing complexity, in Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research Group Functional Verification Study.

Synopsys’ Vadhiraj Sankaranarayanan demonstrates how unique architectural features tailor DRAM for specific applications, in The Importance Of Using The Right DDR SDRAM Memory.

Sponsor White Papers

Timing Is Of The Essence
Variability-aware and SPICE-accurate timing closure.

Closing Functional And Structural Coverage On RTL Generated By High-Level Synthesis
A simpler way to use of machine-generated RTL.