Things to consider in advanced packaging.
Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of different die, and routing of signals.
Sensor technologies are still evolving, and capabilities are being debated.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
Pitches continue to decrease, but new tooling and technologies are required.
Issues involving design, manufacturing, packaging, and observability all need to be solved before this approach goes mainstream for many applications.
Buried features and re-entrant geometries drive application-specific metrology solutions.
Existing tools can be used for RISC-V, but they may not be the most effective or efficient. What else is needed?
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Gate-all-around is set to replace finFET, but it brings its own set of challenges and unknowns.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
High speed and low heat make this technology essential, but it’s extremely complex and talent is hard to find and train.
Work is underway to map heat flows in interposer-based designs, but there’s much more to be done.
Advances in devices, materials, and packaging technologies all contribute to power problems. But do you need to be concerned about each transistor and wire?
Leave a Reply