Power Budgets At 3nm And Beyond

Research is heating up at 3nm, and things are going to be very tight.


There is high confidence that digital logic will continue to shrink at least to 3nm, and possibly down to 1.5nm. Each of those will require significant changes in how design teams approach power.

This is somewhat evolutionary for most chipmakers. Five years ago there were fewer than a handful of power experts in most large organizations. Today, everyone deals with power in one way or another. But at 3nm and 1.5nm, power is about to get significantly more complex for several key reasons.

First, noise will be a pervasive issue. At 3nm, the dielectrics will be less than 10 atoms thick. At 1.5nm, if that node actually happens, there will be even fewer. Layout will require a deep understanding of kinds and sources of noise, such as electromagnetic interference and the power delivery network. There also will be thermal noise from current leakage and dynamic power density. Even the wires will generate heat due to resistance/capacitance. And electromigration at those dimensions could change the dynamics for all types of noise, creating its own set of physical effects.

It’s likely that as transistors hit these dimensions, they will require isolation from other components inside of packages, because shrinking analog circuitry down to 3nm is counterproductive. As a result, noise will have to be considered in multiple dimensions, including how long circuitry is on. One idea that surfaced several years ago is to use through-silicon vias as conduits for electrostatic discharge. It’s possible that TSVs will serve multiple purposes as they are implemented in these packages, both to isolate signals and to shield them from any possible disruptions, whether in 2.5D or 3D-IC configurations.

Second, variation becomes worse at each new node. In the past, this was dealt with through guard-banding, but at 3nm and 1.5nm, guard-banding doesn’t help. The challenge is minimizing everything from electron tunneling effects to signal drift, and variation throws an unknown into the whole process. Just adding more circuitry only adds to the problem.

Variation comes from many sources. It is basically the manufacturing equivalent of what noise is for design. The GDSII handed off to the fab GDSII doesn’t necessarily match what’s printed on a chip for reasons ranging from impurities in the wafer to differences in the chambers of the equipment. All of this has an impact on power at these nodes. That, in turn, has an effect on reliability, because variability can cause latent defects. Add in electromigration and thermal migration across a die and this becomes much more challenging to solve. This is why isolating only those functions that require the most advanced nodes into separate die, and packaging them together, begins to look far more attractive.

Third, one of the benefits of shrinking features is the ability to lower the voltage. It takes less energy to achieve the same functions in digital circuitry if distances are smaller and everything is thinner. But reducing the voltage also reduces tolerances for everything, so devices at 3nm are much more sensitive than at 7nm. Even worse, there are minimum voltages required to retain data in memory. New memory types are being developed to deal with this problem, but it’s too early to tell if they will be sufficiently robust to handle the same number of read/write operations as in the past.

If memories don’t last long enough, the number of operations could be reduced by consolidating operations—essentially getting more per read/write cycle and reducing the overall number of cycles. But this is only at the conceptual stage. There are more questions than answers, and that usually equates to very expensive designs.

Power remains one of the chief sticking points to continued scaling, and from all indications solving power-related problems will only become more critical and difficult at each new node.

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