Why the middle of line is now a major problem.
Klaus Schuegraf, vice president of new products and solutions at PDF Solutions, explains why variability is a growing challenge at advanced nodes, why middle of line is now one of the big problem areas, and what happens when a via is misaligned due to a small process variation.
New architectures, packaging approaches gain ground as costs increase, but shrinking features continues to play a role.
Four industry experts talk about what’s changing, how quickly, and where the limits are with AI.
Work begins on building a quantum computing ecosystem.
2019 will be a year of change for the semiconductor industry as new fields drive technological advancements.
Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
This will go down as a good year for the semiconductor industry, where new markets and innovation were both necessary and rewarded.
Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.
Experts at the Table, Part 1: Impact on the supply chain, who’s using advanced packaging, and the cost of packaging versus device scaling.
Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.
Technology adds more granularity, but starting point for design shifts as architectures cope with greater volumes of data.
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I dare say that design rule “tolerances” might have been scaled prematurely hoping all could be reduced in a new process shrink. Gross oversimplification, BUT crying wolf as “its not working how we thought without probing / characterizing before telling “design rules” committed to might have been optimistic.
Some of the actual design rules curiously might have pattern ?density (local stress?) dependence, not as simple as in larger processes.
Claiming not knowing the sources of the observed variability needs hard data from (design rule) “probing” ?test structures and experiments to pull out the sources and relative error / tolerance magnitudes. We are talking small as each NM is 5 atoms. Just materials “run out” over a 12 inch wafer is somewhat compensated by image field stepper patterning but hardly completely at nm level.
If the via “post” style contacts miss the bottom (target region) of the physical contact, why was this not noticed in Process Development? Was test structure coverage in process characterization too weak, too simplistic?
Sometimes one can only hammer so far on increasing process precision, without rather large yield cost implications. The controversy might be exaggerated, viewed as if everything is solvable by some process fix. It might require design fixes to be pragmatic and expedient albeit sounds like a lot of device designs might have been prematurely committed.
Reminds me of a grad student project at an IVY league mems research team, trying to make lateral reversible mems relay contacts with a sputtering process down high aspect hole and a simple process tool for deposition, when the easy fix might have been with a different architecture ( vertical contacts between actuator on bonded wafer pair )
Oversimplifying a bit. Sometimes the reality is viewed overly complex.
Characterizing design rules early and robustly (with broad case coverage) matters even if boring to some in R&D / TD.