FinFET Metrology Challenges Grow


Chipmakers face a multitude of challenges in the fab at 10nm/7nm and beyond, but one technology that is typically under the radar is becoming especially difficult—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems in devices and processes. It helps to ensure yields in both the lab and fab. At 28nm and above, metrology is a straightforward... » read more

DSA Re-Enters Litho Picture


By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

New BEOL/MOL Breakthroughs?


Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Inside FD-SOI And Scaling


Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more