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Growing Challenges With Wafer Bump Inspection

Co-planarity, variation and data collection emerge as top issues.

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As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and create reliability and yield issues, how much inspection is considered sufficient, and how the data collected from inspection is used.



1 comments

Yasunori Yamaguchi says:

Thank you for very good video discussion.I was agree that problem and inspection technology growing,
100% bump inspection must need future any bump device especially assembly into FAN OUT device.
I think even WLCSP with bump needs 100% bump inspection. but actually OSAT does not check any WLCSP with bump 100% checking. OSAT works only 2D checking for WLCSP. WLCSP also mount into FAN OUT now. I beleive that high speed 3D bump inspection necessary with Die Sorter.

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