Challenges Grow For Creating Smaller Bumps For Flip Chips

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM�... » read more

Bump Height Uniformity And 3D Sensing

Achieving 3D sensing for semiconductor bump height uniformity is essential before adding photoresist. But there are challenges in using traditional methods for measuring uniformity after copper plating, which requires a combination of 3D fringe projection technology and NanoResolution inspection and metrology. Here’s what we’ve learned in a bump height uniformity case study: » read more

Growing Challenges With Wafer Bump Inspection

As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and creat... » read more