FinFET Metrology Challenges Grow

Hybrid schemes are being deployed, with new equipment and machine learning ramping up.


Chipmakers face a multitude of challenges in the fab at 10nm/7nm and beyond, but one technology that is typically under the radar is becoming especially difficult—metrology.

Metrology, the art of measuring and characterizing structures, is used to pinpoint problems in devices and processes. It helps to ensure yields in both the lab and fab. At 28nm and above, metrology is a straightforward process, as the transistor is planar or two-dimensional with larger feature sizes. And with relative ease, chipmakers use a handful of metrology systems to measure structures.

But metrology has become more complex and expensive at each successive node. The challenges escalated when planar transistors ran out of steam, prompting chipmakers to migrate to finFETs. Intel introduced finFETs at 22nm, while foundries moved to finFETs at 16nm/14nm. With this 3D transistor structure the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

While this reduces static leakage, finFETs have an assortment of three-dimensional structures and films that are difficult to measure. In some cases, the structures are well below an angstrom, which is equal to 0.1nm. So the metrology tools must not only obtain two-dimensional measurements, but they must also obtain them in three dimensions in a cost-effective manner. This helps explain why chipmakers require more than a dozen metrology tools to characterize finFETs.

Fig. 1: FinFET vs. planar. Source: Lam Research

At 10nm/7nm and beyond, the metrology community faces additional challenges. For one thing, the finFETs are smaller and packed closer together with new materials entering into the mix. “Now, you have maybe not 10x but maybe 5x more types of metrology techniques (as compared to planar),” said Alok Vaid, deputy director and senior manager of advanced module engineering at GlobalFoundries. “There are more tools in numbers and types. There are more techniques, more data, more cost and more cycle time. It just adds up.”

Moreover, many metrology tool techniques are being stretched to the limit, with noticeable gaps. Fortunately, though, the industry continues to develop new tools and techniques. For example, hybrid metrology and machine learning are moving into the metrology mix.

Metrology challenges
Today’s 300mm fabs are automated plants that process wafers in a step-by-step flow using various equipment. An advanced logic process could have from 600 to 1,000 steps, or more. At various steps, metrology systems are used to measure chips.

A chip consists of three parts—transistor, contacts and interconnects. The transistor serves as a switch for the device. The interconnects consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another. Then, a layer called the middle-of-line (MOL) connects the transistor and interconnect pieces using a series of contact structures.

Fig. 2: Interconnect, contact and transistor at various nodes. Source: Applied Materials.

When the industry migrated from planar to finFETs, the field of metrology changed overnight. “In planar, mostly what you do is measure between two points,” said Mark Wylie, product marketing director at KLA-Tencor. “But in finFETs, you have to measure in 3D. You have the top, middle and bottom. You need to understand the sidewall and these other factors. It’s very involved.”

As finFETs extend to 10nm/7nm and 5nm, the metrology challenges escalate. The finFETs will become smaller and the fins are becoming taller and narrower. “We are seeing taller fins. We are seeing the next challenges of new materials coming in. These are all big challenges for metrologists,” said Ofer Adan, director of metrology and process control at Applied Materials. “Now, we have the 5nm node. There are over 1,100 steps. We have the entire wafer and non-uniformities to deal with.”

There are other challenges. “The complexity due to multi-patterning has led to an explosion in the number of interactions to manage in the transistor technology,” said Klaus Schuegraf, vice president of new products & solutions at PDF Solutions. “The local interconnect directly above the finFET is extremely congested. This leads to tight process windows for dimensional control, with little margin of error. Small variations in dimension or alignment tolerance, coming from the many interacting lithography layers, can lead to significant fluctuation in interconnect resistance — thus limiting transistor performance. Conventional techniques to measure each of these variations quickly exhaust the silicon area available for measurements, due to both the size and the growing number of metrology structures.”

The MOL is also complicated. “It’s very, very complex,” said David Fried, vice president of computational products at Coventor, a Lam Research Company. “You have all the topography of the front-end. The back-end is planar. You’re using materials that are typically less rigid, less stable and less comfortable than you would like to use on the front-end. And then the design constructs present in middle-of-line are much more complex than anything you’d see on the back-end.”

Chipmakers still hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm. “EUV technology is a promising candidate for semiconductor processes at 36nm pitch and beyond. However, challenges remain when considering high-volume manufacturing due to the ecosystem, but also process capability that includes local CD variation, edge roughness and mask selectivity,” said Sophie Thibaut, a process engineer at TEL, in a recent paper at SPIE.

Still, EUV promises to reduce the number of steps in the flow. “The number of metrology steps will likely decrease. But you also have these intra-field effects that you need to take care of to control the edge placement error. So the metrology per wafer intensity will likely increase,” KLA-Tencor’s Wylie said.

FinFET CD metrology
Clearly, chipmakers face a multitude of challenges, particularly in metrology. In planar, chipmakers generally use a trio of metrology tools—a critical-dimension scanning electron microscope (CD-SEM), ellipsometry, and overlay systems.

CD-SEMs, the workhorse metrology tool in the fab, take top-down measurements of the dimensions in a structure. Ellipsometry is an optical technique to measure films. Overlay metrology systems are used to detect shifts in position between the features and layers of a device.

When finFETs were in R&D during the 2000s, chipmakers realized that the existing metrology techniques were insufficient because they provide mostly two-dimensional measurements. But for finFETs, chipmakers require three-dimensional data.

At the time, the industry invested in metrology and met the challenges for the initial finFETs. But chipmakers required more than just three metrology tools. In fact, they require a dozen or more different types.

At 10nm/7nm and 5nm, the number of tool types are increasing, and so are the challenges. “Metrology has always faced two issues—sensitivity and speed,” said Philippe Leray, litho process and patterning control group leader at Imec. “Our problem has not changed. We need to measure smaller and faster. A lot of techniques allow smaller measurements, but the speed seems to be the main bottleneck for the coming nodes.”

For finFETs, chipmakers require metrology tools in five basic categories—dimensional, compositional, dopant, strain, and electrical. Each category consists of several different metrology tool types for the fab. Each group also has different types in the lab.

Fig. 3: Primary metrology techniques presently used in the lab & fab Source: GlobalFoundries/NIST

The first category is dimensional metrology, where a structure requires such various measurements as height, length and width. Planar transistors require five to six measurements, and a CD-SEM can handle these measurements.

In finFETs, though, it requires 12 or more different CD measurements, such as the gate height, fin height, fin width and sidewall angle. The measurements also are conducted at the nanoscale, so it takes more than a CD-SEM to do the job. CD-SEM provides some finFET measurements, but it also has some limitations.

“While conventional CD-SEM demonstrates adequate imaging capability for CD measurement, it has no sensitivity to fin height, layer recess, or SWA (sidewall angle),” according to a recent paper from Vaid and others from GlobalFoundries. (The paper was co-authored by Benjamin Bunday, A. F. Bello and Eric Solecky.)

For finFETs, chipmakers use CD-SEMs, in addition to other tools. But those other metrology tool types also have some limitations for finFETs, as well, so it requires several tools to do the job. “One tool cannot solve all problems,” Vaid said in an interview. “So you may need to utilize two tools and use algorithms and optimizations to measure what you want to measure.”

All told, chipmakers require four different CD metrology tool types for finFETs—atomic force microscopy (AFM), CD-SEM, scatterometry, and transmission electron microscopy (TEM).

AFM uses a tiny scanning probe to obtain measurements. Scatterometry, an optical CD (OCD) technology, measures the changes in the intensity of light. And a TEM transmits a beam through a structure to measure a sample.

CD measurements are conducted at various steps in the fab. Each step may require a different metrology tool type or types. The decision to use one over another depends upon the application, throughput and cost.

For example, a chipmaker wants to measure a finFET. So, what’s the best tool for the job?

Fig. 4: Overall finFET structure and key dimensions Source: GlobalFoundries/TechInsights/NIST

Each technology has its strengths and limitations. As stated, CD-SEMs provide some but not all measurements. AFMs provide high-resolution measurements, but the throughputs are sometimes slow.

Scatteromentry, sometimes called OCD, can measure the CDs, profiles and film thicknesses in finFETs. Scatterometry is fast, but there are some drawbacks. OCD is a model-based technique. In many cases, the tools don’t measure the actual device. Instead, they measure surrogate or simple planar structures, which represent and behave like the actual device. The measurements between these structures and the actual devices are supposed to match or correlate.

Fig. 5: Diagram showing process of generating OCD measurements Source: GlobalFoundries

“That worked for a lot of nodes. It’s not working now, because of 3D devices and variability,” GlobalFoundries’ Vaid said. “When we measure surrogate structures only, we are only measuring 0.01% of the entire wafer. So we run the line through these hundreds of steps. But each of those steps only measure 0.01% or less of the entire wafer. That’s a big problem.”

Indeed, a chipmaker may have multiple parameters. But at times, the correlations between these different measurements may not match. This, in turn, impacts the yield of the device.

OCD faces other challenges. “As devices shrink, the optical volumes of some of the critical features are becoming extremely small, for example, with top corner rounding or undercuts. Thus, sensitivity to these parameters is lost, which compounds with the cross-correlation problems,” according to the paper from GlobalFoundries’ Vaid, Bunday, Bello and Solecky.

Ideally, chipmakers want to measure the actual structure, not proxy targets, with OCD. Suppliers of OCD tools are making progress here. “OCD suppliers are doing a good job innovating,” Vaid said. “They will have to evolve even further, maybe a revolutionary improvement than an evolutionary one.”

All told, CD metrology tools can handle some but not all finFETs measurements. So what’s the best solution? In some cases, a standalone tool may work. Generally, though, metrologists tend to use a combination of two or more tools for a given parameter.

This is called hybrid metrology. For example, a certain step may require a combination of AFM, CD-SEM and OCD. Typically, a CD-SEM works with OCD, or AFM with OCD. Then, you take the information from two or more tools and combine them to obtain better results. “The word ‘hybrid’ has been excessively used and for different meanings,” Imec’s Leray said. “The easiest and widely used one in the industry is feedforward or feedback. A tool is feeding a measurement to another one to stabilize the solution of the second. It can also be used when you feed a model with different metrology to predict process behavior. It can also drive another technique.”

Meanwhile, there is another solution—TEM. TEM enables users to measure the actual structure, but it’s a time-consuming and a destructive technique. A user must cut the wafer and examine the cross-section of the structure using a TEM.

For that reason, TEMs have been used in the lab, but that’s changing. “The TEM gained significant traction with the transition to finFET because it provides an atomic-scale sub-surface perspective of these complex three-dimensional structures,” said Jack Hager, senior product marketing manager at Thermo Fisher Scientific. “As one might anticipate for finFETs, TEM-based metrology continues to focus on fin formation, epi growth and gate formation in the front-end as things scale smaller.”

As a result of these capabilities, TEMs are invading the in-line flow and will likely become part of the hybrid metrology equation. “Subtle process effects that can be captured by TEM metrology can be highlighted to other metrology systems for their benefit,” Hager said

Film metrology challenges
Besides CDs, there are also challenges in the other four segments in the metrology arena- compositional, dopant, strain, and electrical.

The compositional segment involves film thickness measurements and the composition of films. For this, chipmakers use an advanced form of ellipsometry. The tool, called a variable-angle spectroscopic ellipsometer, measures wavelengths from the ultraviolet range to near infrared.

In addition, chipmakers use various X-ray techniques for the composition of devices, such as X-ray photoelectron spectroscopy (XPS). “(XPS) is slower than optical tools, but it’s faster than some of the lab tools. The accuracy is great. The problem? It still measures planar surfaces,” GlobalFoundries’ Vaid said. “But we have been doing a lot of work with our supplier to be able to measure on the structure. We can do some measurements. As long we keep going on that path, we think there is light at the end of the tunnel, where we can actually measure in 2D and 3D.”

Besides XPS, chipmakers use other X-ray tools in the composition segment—X-ray diffraction (XRD), X-ray reflectivity (XRR), and X-ray fluorescence (XRF). XRF determines the elemental compositions of materials. XRR handles thin-film measurements.

XRD, which is used to explore single-crystal and thin films, is also used for both composition and strain materials in devices. Then, for dopants, some use low energy electron induced X-ray emission spectrometry (LEXES).

Many X-ray tools are niche solutions. “They do great for one, two or three killer applications. It has a slow throughput,” Vaid said. “The problem with some of these X-ray tools is the light source. The X-ray source does not have enough brightness to be able to reduce and scale towards the volumes we want.”

New solutions
Clearly, the metrology community faces several challenges with some noticeable gaps. Fortunately, the industry is developing new solutions.

The industry continues to make incremental improvements with CD-SEMs. But in what could propel the CD world, Applied Materials and ASML are developing a new class of e-beam metrology tools called massive CD tools. A massive CD tool is a souped-up e-beam inspection system with CD-SEM and overlay capabilities.

For years, meanwhile, the industry has been developing small angle X-ray scatterometry (CD-SAX). Using an X-ray source, CD-SAX measures pitch variations.

Fig. 6: CD-SAX Source: NIST, Lam Research

CD-SAX is supposed to replace OCD, but that hasn’t happened. CD-SAX works, although the X-ray power source is still not adequate and the spot size is an issue for logic.

Instead, CD-SAX is finding a place in memory. At SPIE, Lam Research and NIST presented a paper on using CD-SAX for amorphous-carbon hardmasks. “With CD-SAX, we have the ability to measure 2D and 3D profile information,” said William Thompson, an engineer at Lam, in a presentation at SPIE. “Amorphous-carbon hard masks play a role in memory. So, you have new metrology needs that we need to satisfy for the validation of these structures that result in the process. So, CD-SAX with no material property assumptions has been able to show accurate structures across the wafer.”

Another technique is also making its way in metrology—machine learning. “Machine learning is an emerging technique, where you use algorithms to solve some of the challenges and hone in to the metrology parameters,” GlobalFoundries’ Vaid said. “It’s in the feasibility stage. It’s being deployed for 7nm and beyond.”

In a recent paper from GlobalFoundries and Nova, the companies investigated the use of machine learning as a complementary method to OCD. Using machine learning, researchers demonstrated the ability to predict the fin CD values from inline measurements. Researchers also predicted the electrical resistance in interconnects using data from both OCD and electrical tests.

Machine learning won’t replace metrology tools, but it could help solve the most difficult challenges. To be sure, chipmakers will still require a plethora of metrology tools at 10nm/7nm and beyond. Clearly, the challenges will keep metrologists busy, if not awake, for the foreseeable future.

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Allen Rasafar says:

Thank you for sharing this in depth article. I was called the father of Massive CDU in Global Foundries. I used multiple set of tools including AMAT eBeam to develop an advanced CD and pattern fidelity measurement tool. With new method we were able to collect millions of data point, and assess Full patterning metrics within an hour using new eBeam tools with sub nanometer resolution. There are other complementary methods that are more promising but technologist are not fully aligned on using the BKM that I introduced 2 year ago. I suggested a new platform and metrics for measuring sub 10nm/7nm technol0gy nodes. Current metrology which is based on generation of the older metrology is not very well suitable for advanced technology nodes and we have tremendous volumes of data to prove it.

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