Searching For EUV Defects

What issues remain, and how they could affect manufacturing at 7/5nm.

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Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this oft-delayed technology can be used in production.

One lingering issue that is becoming more worrisome is how to find defects caused by EUV processes. These processes can cause random variations, also known as stochastic effects. These effects, in turn, cause stochastic-induced defects, such as pattern roughness and faulty contacts in chips.

That isn’t the only issue, though. The industry continues to develop the source power and EUV masks. But stochastics is the top challenge because EUV stochastic-induced defects are often catastrophic and can cause chip failures. So it’s imperative to find and prevent these defects to ensure that EUV lithography moves into production at 7nm and/or 5nm.

The problem is that for stochastic-induced defects, the industry knows where the problems start, but it doesn’t have a complete understanding why it happens. Nor can it predict the outcomes. Plus, the industry doesn’t have all of the techniques in place to locate and measure EUV stochastic-induced defects.

Today, the industry uses various metrology and inspection tools to locate and measure defects in chips. But current methods may fall short when it comes to EUV stochastic-induced defects. So either solutions are developed, or EUV lithography may not get off the ground.

Fortunately, several new and promising metrology/inspection solutions are emerging in both the lab and the fab. In the lab, the industry is gaining new insights using exotic X-ray techniques powered by giant synchrotron storage rings. Then, in the fab, tool vendors are developing new e-beam metrology systems and software technologies.

To help the industry gain an insight in the arena, Semiconductor Engineering is taking a look at the status of some of the metrology technologies in both the lab and fab.

Locating the problem
As before, GlobalFoundries, Intel, Samsung and TSMC hope to insert EUV lithography at 7nm and/or 5nm. Chipmakers need EUV because it’s becoming more difficult to pattern the critical features in chips.

ASML, meanwhile, is shipping its first production EUV scanner. In EUV, a power source converts plasma into photons at 13.5nm wavelengths. Then the light bounces off a scheme of 10 multi-layer mirrors. At that point, the light hits the mask and moves toward the wafer.


Fig. 1: Accurately bouncing light. Source: ASML/Carl Zeiss SMT Gmbh.

Then, the photons hit a photoresist, causing a chemical reaction. Resists are light-sensitive polymers used to create patterns in devices.

In today’s 248nm and 193nm wavelength lithography, chipmakers use chemically amplified resists (CARs). In the process, the photons hit the CAR, generating an acid. The CAR subsequently undergoes an acid catalyzed reaction during a post-exposure bake process.

In EUV, the reaction is different. First, EUV photons (92eV) contain 14 times more energy than 193nm photons (6.4eV). Then, for the same exposure dose, there are 14 times fewer photons.

In the EUV process, the photons are absorbed by the resist, which generates electrons. These electrons cascade into secondary electrons, which hit a photoacid generator to generate acids. Then, the resist is baked and the acids diffuse through the material changing.

This chemical reaction is where the stochastic problems start. But the big issue is that there are various unknowns about these reactions. “The industry does not yet have a full physical chemical understanding of the exposure reaction mechanisms, as it is a complex process with a handful of unknowns,” said Gregory McIntyre, director of the Advanced Patterning Department at Imec.

According to Imec, here are a couple of the unknowns. First, there are variations in terms of how many photons are absorbed in the resist during the reactions. And second, there are variations regarding how many electrons are created, as well as their energy levels.

So, when EUV exposes the resist, the result may be different in each event. This unwanted result is known as stochastics.

In EUV, photons hit the resists in multiple and consecutive events. Each event might be different. The variation from one event to the next is a phenomenon called photon shot noise.

Both stochastics and shot noise are problematic. “The industry is saying that EUV will start in production at 7nm, at least for limited use. But there seems to be an increased general perception that shot noise will soon be an issue with EUV,” said Aki Fujimura, chief executive of D2S.

The actual defects are caused by stochastic effects and the problems mount at each node. “The numbers of defects go up drastically as the feature sizes go down, so the problem will be much, much worse when we scale down from 7nm to 5nm,” said Chris Mack, CTO of Fractilia.

There are other issues. “The imaging needs a good match between the substrate layer and the resists,” said James Lamb, deputy CTO and corporate technical fellow at Brewer Science. “The challenge has been how to get past the stochastic effects, LER and LWR, as well as how to make everything thinner.”

This is a complex problem. “The goal here is to decrease the number of defects and stochastic effects, and that requires you to spend more time tuning the underlayers,” said Lamb.

Finding the defects is a daunting task, but it is not the only challenge. “It’s not just the number of defects, but also finding the defects at the right point is a huge challenge today,” said Richard Wise, technical managing director at Lam Research. “The problem is that in the resists, a lot of times the defects are harder to see, because the contrast between the resists and what’s underneath is not as clear. There is an issue where the resist is perhaps under-exposed. There are not enough photons. They are smaller and you are trying to find them where there are lines and bridges between it.”

What’s the bottom line? “It takes days to find that one missing pattern. And that one missing pattern, in the logic case, will kill your device,’’ Wise said.

In the lab
The industry is looking at the problem from several angles. Generally, in the lab, the goal is to characterize the materials and gain a better understanding of the chemical reactions between the photons and resists.

For this, the industry uses various measurement techniques. In a paper presented last year, for example, the Advanced Research Center for Nanolithography (ARCNL) studied the reactions of metal-containing hybrid inorganic materials used in EUV resists. Metal-containing resists have higher sensitivities than CARs, but they are not fully understood.


Fig. 2: Molecular structure of a tin-oxo cage compound in EUV resists. Source: ARCNL

To gain some insights in these mechanisms, ARCNL used a metrology technique called hard X-ray photoelectron spectroscopy (HAXPES). This technique probes the electronic properties in materials. (See link below for the paper.)


Fig. 3: The HAXPES spectrometer. Source: HZB

In this case, HAXPES is powered by a synchrotron light source from Helmholtz–Zentrum Berlin (HZB). A synchrotron light source is a large circular ring, which generates radiation from the terahertz to the X-ray spectrum.


Fig. 4: Electron storage ring BESSY II. Source: HZB

For its part, Imec uses similar X-ray techniques to study absorption and yield in EUV resists. Imec also uses other electron spectroscopic techniques for chemical analysis. “Each technique measures specific things, but none of them gives you the full picture of what actually happens inside of a resist during exposure. The challenge is to put all the information together into a complete model that will aid in material design,” Imec’s McIntyre said.

So the industry needs new solutions. “In EUV, the chemistry of radiolysis is governed not just by energy, which we usually study, but also by quantum effects, such as orbital angular momentum,” McIntyre said. “To gain a full understanding of these effects and processes, we need to apply ultra-fast transient spectroscopic/3D imaging and molecular modeling techniques. These detect, measure, image and interpret ionization processes that occur on the atto-/femto-/pico-/nano-second time scales as we move from atom-localized events at higher core electron energy levels, from 92eV to 30eV, to delocalized molecular events at lower valence electron energies where final chemistry occurs.”

Obviously, it’s impractical to install a storage ring in a fab, as they are too expensive and present some safety concerns.

Taking another approach, the Paul Scherrer Institute (PSI) studied the chemical reactions using its X-ray Interference Lithography (XIL) beamline. This technology provides a spatially coherent beam in the EUV energy range.

This work presents an experimental method to measure secondary electron blur (SEB) from a lithographic point of view. “EUV light, upon absorption in the photoresist, generates secondary electrons, which in turn induce chemical reactions. The effective travel range of the electrons is the SEB,” said Yasin Ekinci, group leader of advanced lithography and metrology at PSI. “The light-matter interaction is fundamentally different than for DUV wavelength. In fact, the mechanism is similar to that of e-beam lithography where secondary electrons can travel several microns. For EUV this is a few nanometers. SEB is not a bad thing in general. It can become a limiting factor for resolution. But we need also sensitivity which is proportional to the volume of interaction which is limited by the SEB. This is then a new version of RLS tradeoff.”

Recent works estimate that a cascade of 2-4 electrons is generated, on average, per absorbed EUV photon. “I think that experimental and theoretical estimation of the number of generated electrons per photon is not only very difficult but also vague. We should talk about number of ‘useful electrons,’ such as the average number of secondary electrons that induce a chemical change,” Ekinci said.

What did PSI find in the experiment? “Since it is practically impossible to gauge what is happening in the resist, one has to come up with indirect ways. In a recent study, we did this by measuring resist thickness loss upon EUV exposure and development. We compared these values for two cases, one with a transparent substrate and one with a highly absorptive substrate. The idea is the observe the residual resist that is close to the substrate should change if some electrons generated in the substrate travels into the resist,” he said. “In conclusion, we calculated the secondary electron blur about 2nm. In a different study, we measured the volume of resist cleared per absorbed photons. For non-chemically amplified resists we measured a sphere of about 2nm in diameter. Two completely different approaches gave the same results.”

Solving LER
Besides the lab, there are challenges in the fab. Stochastics in EUV processes tend to produce features with pattern roughness. In fact, the edges of the features are sometimes rough, which is called line-edge roughness (LER). LER describes variation on the edges of the features.


Fig. 5: Line-edge roughness (LER). Source: Lithoguru, Fractilia

LER is problematic. First, it can impact the performance of a transistor. Second, LER doesn’t scale with the feature size. At 10nm and below, these variations may become as large as the features on the chip itself, according to Fractilia.

Some use a critical-dimension scanning electron microscope (CD-SEM) to measure LER. A CD-SEM takes “top-down” measurements of the CDs, such as width and height, of a structure. To do this, it sends out an electron beam into a sample, which interacts with electrons in the structure. Then the signals are sent back and mapped in the system.

For LER measurements, the idea is to detect issues at the edge of a pattern. The recommended LER metric is defined as the 3-sigma of residuals measured along a 2μm-long line, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.

The current methods are limited. “At 10nm and below, semiconductor engineers need to have a clear picture of the impact of pattern roughness on process and device performance,” Fractilia’s Mack said. “Yet, they have not been able to get that picture with existing tools and technology.”

At times, the signal-to-noise ratio in a CD-SEM become an issue. It produces CD bias, which is the difference between the actual and measured values.

To solve the problem, Fractilia recently introduced a software tool for measuring LER. It works with CD-SEMs from various vendors. Basically, Fractilia’s technology separates the CD-SEM errors caused by bias. Then, it predicts the impact of roughness.

Typically, the CD-SEM produces images or linescans of a sample using the analytical linescan model (ALM). “Fractilia’s software does not use the ALM directly. Instead, it inverts the ALM. This is used to detect the edges of all the feature in the SEM image. This is the first step. The second step takes the detected edges and calculates the PSD. The hard part is detecting the edges from a noisy SEM image,” Mack said.


Fig. 6: Fractilia’s technology measures pattern roughness.

Calculating the power spectral density (PSD) is key. “The PSD is a mathematical technique to statistically characterize a rough edge,” he said. “The PSD gives you more than just the 3-sigma. Full PSD analysis also shows you how much of the roughness is in the low frequency regime and how much is in the high frequency regime. So, think of PSD as a superset of information, which includes 3-sigma, but also other information.”

In other words, the 3-sigma metric is insufficient to understand LER. “Line-edge roughness characterization can no longer be limited to an average standard deviation number,” said Angélique Raley, etch process development manager at the Tokyo Electron Technology Center of America, part of TEL.

“A more in-depth understanding of the roughness along the frequency domain is indispensable to understand roughness propagation from lithography to the etched underlying stacks. Understanding whether the low-, mid- or high-frequency domain is driving the roughness changes throughout the process is key to identifying and addressing the root cause of this change,” said Raley, who was quoted in a recent product release from Fractilia.

Missing/kissing contacts
Now, Fractilia and others are addressing the next challenge—contact hole failures. A leading-edge logic chip incorporates a billion or more tiny contacts. If there is a mishap in the EUV process, the contacts could suffer from stochastic-induced defects. A chip can fail with a defect in just one contact.

A faulty contact might consist of an unwanted micro-bridge or two contacts could end up merging. This is called “missing or kissing contacts.”

“At 45nm, you knew a defect was caused by the design and in a specific location. With EUV, the defects are more random, and that’s a big challenge,” said Neeraj Khanna, senior director of worldwide customer engagement at KLA-Tencor. “All of that requires more process control, and a lot of this comes back to basic yield control. With debug, you need to find as many defects as possible. But what you really need to do is find the source of the defects, and that needs to be done in a very small process window at 7nm versus 16nm/14nm.”

There are other challenges. “It’s not just a missing or a kissing contact. You need to see if you can replace a block layer that is sitting over an SAQP array with EUV. Can you look at block layers that you used to print with many masks and now you are printing with an EUV mask, and solve all the problems,” said Ofer Adan, director of metrology and process control at Applied Materials. “You need to check not just the block CD, but also block placement. It’s a problem with CD and overlay. It’s what we call edge placement error.”

All of this presents a headache in the fab. In theory, a chipmaker must sample every chip on a wafer to look for faulty contacts. To handle these daunting tasks, the industry needs a metrology tool that can take millions, if not a trillion measurements.

So in response, Applied Materials and ASML are developing a new class of e-beam metrology tools, or so-called massive CD tools. A massive CD tool is a souped-up e-beam inspection system with metrology capabilities, such as CD-SEM and overlay.

CD-SEMs measure structures in a small field of view. Meanwhile, e-beam inspection is used to find the smallest defects in chips, as it has sensitivities down to 1nm. E-beam inspection is slow.

E-beam metrology combines the best of both worlds. A toolmaker takes an e-beam inspection system and adds image measurement algorithms from a CD-SEM, enabling the machine to take measurements in a full field of view.

“You make the e-beam tool faster. And you make thousands and millions of measurements per wafer in a short duration of time,” said Alok Vaid, deputy director and senior manager of advanced module engineering at GlobalFoundries. “It’s still an e-beam, but you can take a bigger field of view. When you take a bigger field of view, you can see more within that shot. You have enough resolution and enough imaging tricks to apply the CD-SEM measurements. And then you use design information to help you. That helps you measure quickly.”

This tool has some limitations, at least right now. It provides some but not all CD and overlay measurements. It handles millions of measurements, but the industry wants a tool than can handle a trillion.

Putting it together
Still, these tools will provide valuable information, but there is one problem—the industry must deal with an explosion of new metrology data.

The next task is to take this metrology data and funnel it into the various process tools in the fab. The lithography tools are ahead of the game. They are able to collect mountains of data and have the knobs in place to tune the process.

Many other fab tools don’t have all of the knobs in place. “We want the metrology suppliers to be working with the process suppliers on knob development,” Vaid said. “Our key message is that we want them to work together.”

It’s unclear how long that will take or how will they accomplish it. But if the industry drags its feet, EUV may slip again. And that’s something no one wants to see happen.

Related stories
EUV’s New Problem Areas
Photochemical conversion of tin-oxo cage compounds studied using hard x-ray photoelectron spectroscopy
Looming Issues And Tradeoffs For EUV
More Lithography/Mask Challenges
Why EUV Is So Difficult
Unsolved Litho Issues At 7nm
Challenges Mount For Photomasks
Survey: Optimism Grows for EUV



1 comments

Guest says:

Thermally-induced EUV aberrations are still not taken care of.

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