Challenges Mount For Photomasks

Optical proximity correction, EUV pellicles, inverse lithography and actinic inspection make it hard to achieve a return on investment at advanced nodes.


Semiconductor Engineering sat down to discuss photomask technologies with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); Banqiu Wu, principal member of the technical staff and chief technology officer of the Mask and TSV Etch Division at Applied Materials; Weston Sousa, general manager of the Reticle Products Division at KLA-Tencor; and Aki Fujimura, chief executive of D2S. What follows are excerpts of those conversations, which took place as a series of one-on-one interviews.

SE: What are the big challenges in the overall photomask industry today?

Hayashi: Return-on-investment and cost, especially for merchant mask shops. It’s unclear if the industry can get an ROI along with increasing capital spending.

Sousa: We see two primary trends in reticle technology at the 10nm node and beyond. The first is complex optical proximity correction (OPC) on reticles for 193nm lithography. To extract the last bit of litho performance from 193nm immersion scanners, almost all leading node customers are using aggressive OPC, such as inverse lithography technology (ILT), for at least a portion of the reticle. Mask writing time has significantly increased, which drives demand for multi-beam mask writers. On the inspection side, complex OPC generates massive numbers of real but lithographically insignificant defects. The challenge for reticle inspection is to handle the massive number of nuisance defects while not missing a single defect that is lithographically significant.

SE: What is the second trend?

Sousa: The second is the introduction of reticles for extreme ultraviolet (EUV) lithography. All leading-node IC manufacturers and mask shops are experimenting with EUV lithography and reticles. The exact insertion timing of EUV lithography in production is still uncertain, but the mask sector is ramping up efforts on the development of EUV reticles. The challenges are numerous, from blank quality and CD uniformity to pattern defectivity and repair.

Fujimura: In general, EUV lithography continues to make significant progress. Its migration to production will heighten the need to address EUV mask requirements and emerging challenges, such as EUV pellicles, mid-range effects, shadowing and mask inspection. At the same time, the increased need for precision on the mask, whether for 193i, EUV or nanoimprint lithography, is impacting turnaround times. The mask industry is looking forward to the improvements in both mask turnaround times and precision that will come from multi-beam mask writing machines.

SE: Let’s start with EUV lithography. Is the EUV mask infrastructure ready or not?

Fujimura: The mask infrastructure can be made ready for EUV. But ‘can be’ and ‘is’ are different things. Furthermore, learning to use each new technology that is needed in the mask infrastructure, and then learning to integrate them into an operational flow for high-volume manufacturing of EUV masks, still requires investment and time.

Hayashi: Eighty percent is ready except for the defect assurance technologies, such as inspection and the pellicle.

Wu: In the last few years, a lot of new things have been added to the EUV mask infrastructure. And in the last few years, people have been talking about actinic inspection. Now, the topic is the EUV pellicle. For the pellicle, the industry has made good progress. So far, many of the key issues have been addressed, but there are still some issues. For example, if you have an EUV pellicle, it’s so easy to break it. The question is how to handle and use it.

SE: In the EUV mask production flow, the first step is to develop and manufacture an EUV mask blank. What are the challenges here?

Fig. 1: EUV mask blank. Source: GlobalFoundries

Sousa: An EUV blank is significantly more complex to build than an optical blank, given more stringent requirements for flatness, defectivity, and absorber film quality. An EUV mask blank is typically composed of 40 multi-layer pairs of molybdenum/silicon (Mo/Si) material that is deposited by the blank manufacturer. This is capped by a layer of ruthenium, followed by the deposition of a tantalum-based absorber. Any particles added during any of these steps have the potential to create height deviation in the stack, which can be the source of so-called phase defects. In addition, at the substrate level, any irregularities like bumps or pits in the doped quartz can propagate through the film stack to become phase defects.

Wu: The key defect is the phase defect. Phase defects are mainly contributed by the substrate. That means if we want to solve the problem, we almost need a perfect substrate. That means the substrate has no pits there. The challenge is for the inspection tool to find them.

Fig. 2: EUV photomask (Source: University of Hyogo)

SE: EUV mask blanks have defects, which are caused during the production phase of these products. Therefore, the blanks need to be inspected. The industry is developing both optical and actinic inspection for EUV mask blanks. Using the same 13.5nm wavelength as EUV, actinic inspection can supposedly find more defects than traditional optical inspection. So what’s the best solution here?

Hayashi: Only actinic inspection can catch the phase defects. Optical inspection can catch the amplitude defects with certain pit and/or bump sizes on the blank surface.

Wu: If you have a very shallow pit, it’s very difficult to use optical to identity all of them. Maybe you miss some of them. After you do the coating, we can use actinic. But so far, that’s one of the main challenges.

Sousa: There remains the challenge of detecting and hiding phase defects, which must be done before mask writing. We expect that at least for the initial ramp of EUV there will be some number of phase defects that must be placed under the absorber during the mask patterning process.

SE: After the EUV mask blank is developed, the next step is to pattern the blank. Traditionally, mask makers use single-beam e-beam tools to pattern or write the features on a photomask. Single-beam e-beam tools are based on variable shape beam (VSB) technology. But the write times continue to increase for the most complex masks. Now, however, the industry is developing multi-beam mask writers to speed up the write times. Do we need multi-beam mask writers for EUV, optical or both?

Fig. 3: Multi-beam Uses Many Beamlets in Parallel Source: IMS

Fujimura: The need for multi-beam mask writing is often tied to EUV production. Curvilinear inverse lithography technology, which enables better process margins on the wafer for small shapes, is also enabled by multi-beam. Because of this, some may elect to use curvilinear or ILT for 193i at 7nm, and use multi-beam mask writing. However, the general thinking is that VSB is sufficient for 193i masks.

Hayashi: There are a huge number of shot counts and data volumes for EUV masks as well as optical masks with ILT. In addition, slow and high-resolution resists are needed for nanoimprint lithography masks. In all cases, without multi-beam technology, patterning turnaround times and quality may not be feasible. Fortunately, high-volume manufacturing multi-beam tools are in the field for the actual production phase for 7nm. Additional tools will be available this year.

Fujimura: Multi-beam provides a constant write time for a given resist, regardless of the shape count on the mask. This affords so much more flexibility to enable much more complex and smaller shapes to be written with the same resist on the mask than was practically possible before. While today’s masks are written in reasonable times without multi-beam writers, having the multi-beam mask writers opens up a whole new set of possibilities for patterns that can be written on the mask. Curvilinear lines or straight diagonal lines of any angle can be written with smaller minimum widths in practical write times with multi-beam mask writers with the same resist. This kind of capability enables multi-beam mask writers to be better for writing curvilinear ILT patterns for better 193i performance, and better for writing any-shape EUV patterns, even including EUV with ILT.

SE: Once the EUV mask is patterned, the photomask is inspected for defects, sometimes called pattern mask inspection. Today, traditional optical-based inspection tools are being used to find defects for both optical and EUV patterned masks. But optical may run out of steam in terms of resolution, prompting the need for actinic technology for pattern mask inspection. Do we really need actinic or can optical do the job?

Sousa: New optical and algorithm technologies enable our (optical-based inspection) platform to fully meet the pattern reticle inspection requirements of first-generation EUV reticles for HVM.

Wu: If we have actinic, it’s better. But to do this, the cost is pretty high. So instead, some people believe we can control the blank. For example, if we do good inspection on the EUV mask blank before absorber deposition, and after the pattern is formed, we may not need actinic. We’ve already used actinic blank inspection after multi-layer deposition. That one is easier, because there is no pattern influence. When you do pattern inspection, it’s difficult to do that on the pattern edge and to define the defects. That could make inspection very slow. One inspection could take several hours to do it.

SE: Is there another solution for EUV pattern inspection?

Sousa: Timed to intersect with the insertion of EUV into production implementation, we are developing a multi-column e-beam mask inspection system that simultaneously meets requirements for cleanliness, sensitivity, and production-worthy throughput. We believe that a combination of high-sensitivity e-beam mask inspection prior to pelliclization and a lower-cost, optical-wavelength post-pellicle solution provides the best solution for overall performance and cost.

SE: In many cases, though, the industry wants actinic inspection for patterned EUV masks. The problem is that technology does not exist today. It would take several years and $500 million or more in funding to develop a production tool. There is also a return-on-investment issue. For example, there are only a few mask shops that are making EUV photomasks. And so only a few customers would need an actinic tool, meaning the market is limited, right?

Wu: It’s not only for inspection, but for the whole mask industry, including the mask writer, mask etch and mask inspection. All of these mask fabrication tools have a similar problem. The mask industry has a small market size, but there are very high challenges in terms of the technology.

SE: According to a recent survey from the eBeam Initiative, overall mask yields are at a healthy 94.8%. That includes optical masks. EUV mask yields, however, are about 64.3%, according to the survey. That figure must improve, right? Where are we in yields and defect density for EUV masks?

Fujimura: As you get to the leading-edge, the more difficult it becomes for mask makers. Partly, for EUV, I’m sure a lot of this is just a lack of experience. I am sure that the industry will have to go up the yield curve.

Wu: If you look at the whole mask industry in terms of yields, some people say it’s like 80% or 90%. That’s actually the average value. But if look at the high end, mask manufacturing yield could be very low, definitely below 50%.

Sousa: In the IC fab, the ultimate arbiter of reticle defect relevance is whether or not it prints on the wafer. Given the challenges of EUV lithography, wafer print is growing in importance for detecting defects that originate on the mask, or as a result of the interaction between the mask and the process window. So-called repeater defects are detected on the wafer using optical-wavelength wafer inspection systems, and then traced back to the reticle. With extremely small process windows at the developing device nodes, we have found that some of these defects print inconsistently from one die to another. The same pattern types—those most sensitive to process window fluctuations, termed hotspots—may print inconsistently even within the same die. In order to capture these defects on the wafer, the speed of a broadband plasma optical wafer inspection system is important in order to get the coverage needed, in cases where sporadic print fidelity errors occur.

SE: Let’s move to optical masks. What are the big challenges here or for mask making in general?

Wu: Optical lithography has been limited. That means that the mask’s primary features are like around 80nm and the assist features like 40nm. These kinds of things have not changed. Actually, the real change for the mask maker is that the processes must become more and more accurate.

Fujimura: Turnaround time is obviously related to data volumes and also the write time. Turnaround time includes everything. It is mask writing, inspection and repair. It starts with data preparation. In turnaround times, leading-edge nodes are much worse than the trailing-edge nodes. It’s not surprising, but by how much is very telling. Not only are mask turnaround times taking longer, but the number of masks is increasing by a lot. Of course, the number of critical layer masks is not going up by that much. It is going up by the triple and quadruple patterning of the critical layers. Still, it’s going up enough to make it a much more difficult job for the mask shops. You have to do things better but you have to do things faster too. That’s very hard to do.

SE: What are some of the metrology challenges with optical?

Wu: For optical, we divide one pattern into several layers. That means you use several masks for one layer. That means it could create a location error. This kind of error should be controlled very tightly. Otherwise, the masks do not match. So alignment, or having the different layers in the right position, is critical.

Sousa: Reticle quality is directly linked to wafer yield. When we talk about reticle quality, we refer to two aspects: (1) defectivity – a reticle defect will be replicated on every die on a wafer as a pattern defect, thus directly impacting device yield; and (2) parametric uniformity, such as critical dimension (CD) uniformity and pattern placement error, which is also known as pattern registration error. The inability to achieve strict parametric uniformity specifications can significantly reduce the process window in lithography, resulting in poor device yield. To comprehensively characterize reticle pattern registration error at leading-edge design nodes, mask shops are migrating from sampling a few hundred registration targets on the reticle, to much higher sampling on actual circuit features. These in-die measurements provide significantly more information on reticle pattern placement error. These data provide critical feedback to the e-beam mask writer, with the higher data density enabling unique qualification capability for multi-beam mask writers. The in-die pattern registration measurements also provide information on the overlay of one mask to another, which is critical to meeting the tighter registration requirements of multi-patterning lithography.

SE: Inverse lithography technology (ILT) is a next-generation reticle enhancement technique (RET) that enables an optimal photomask pattern for both optical and EUV reticles. Using a complex mathematical formula, ILT improves the latitude of a process and the depth of focus for a lithography tool. Where is ILT today? Will full-chip ILT ever happen?

Fujimura: ILT is definitely here today. However, the definition of what makes a mask an ILT mask versus an OPC mask varies greatly depending on whom you ask. The universal understanding is that ILT is a form of advanced reticle enhancement technology (RET). Some define ILT by the method of computing, and others define ILT by what the resulting mask looks like with more complex patterns. In any case, it is my personal belief that ILT should be GPU-accelerated. Since ILT’s greatest issue is run-time, it seems to me that GPU-acceleration is the natural answer.

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Mask Maker Worries Grow—Part 1
Gap widens between economic returns and the amount of R&D required to fully utilize next-generation lithography.
Mask Maker Worries Grow—Part 2
Problems continue to grow at each new process node, and so do the costs.

  • memister

    multi-beam writing tools already in the field?

    • Mark LaPedus

      IMS has three in the field (Intel, TSMC and DNP). NuFlare has a beta tool, reportedly at Samsung.

      • memister

        Interesting, thanks!