Mask Maker Worries Grow

First of two parts: Gap widens between economic returns and the amount of R&D required to fully utilize next-generation lithography.


Leading-edge photomask makers face a multitude of challenges as they migrate from the 14nm node and beyond.

Mask making is becoming more challenging and expensive at each node on at least two fronts. On one front, mask makers must continue to invest in the development of traditional optical masks at advanced nodes. On another front, several photomask vendors are preparing for the possible ramp of masks based on extreme ultraviolet (EUV) lithography technology at 7nm and/or 5nm.

Optical and EUV photomasks are different. Both mask types can be produced using some of the same tools, but EUV masks require additional new and expensive equipment.

Several mask makers will end up producing photomasks based on both optical and EUV. Regardless of the technology type, photomask makers will require vast resources, know-how and a range of new equipment and materials.

To find out what’s required for future masks, Semiconductor Engineering recently conducted an informal poll among several photomask makers and experts in the field. The poll asked experts to come up with a “wish list” of technologies that are required for future mask making. Some respondents wanted to remain anonymous, while others were willing to discuss the issues.

Based on the poll, there are needs for nearly every part in the mask supply chain:

  • Most respondents said there is a need for three technologies—actinic inspection, multi-beam mask writers, and new mask metrology tools.
  • Other technologies made the list, as well, such as defect-free EUV mask blanks and EUV pellicles. New cleaning systems, repair tools and resists also made the list. And one respondent sees a need for new 200mm mask tools.
  • Economic issues are also on the minds of mask makers. One respondent believes that mask makers need to raise their prices as a means to boost their margins.

Some of these technologies are already in the market. Still others are in R&D and may soon appear in the mask shop. But not all technologies will make it into production.

(Semiconductor Engineering will examine the status of these “wish list” technologies and issues in a two-part series. Part one looks at EUV mask blanks, multi-beam mask writers and inspection. Part two will look at other technologies.)

The photomask is a critical part of the IC supply chain. A chipmaker designs an IC, which is then translated into a file format. Then, a photomask is developed based on that format.

The photomask is a master template for a given IC design. After a mask is developed, it is shipped to the fab. The mask is placed in a lithography tool. The tool projects light through the mask, which in turn patterns the images on a wafer.

All told, the success of a given IC design revolves around the mask, although the photomask makers themselves don’t necessarily reap the rewards or profits in the scheme of things. The photomask industry is a tough and competitive business. In total, the photomask market reached $3.4 billion in 2015, up 1% over 2014, according to SEMI. The mask market is expected to grow 2% and 3% in 2016 and 2017, respectively, according to SEMI.

In addition to lackluster growth rates, mask makers face other challenges. For example, mask makers must invest huge sums of money to develop complex masks at each node. Generally, though, the average selling prices (ASPs) for leading-edge masks are trending up, but not as fast as R&D costs. Mask customers are generally unwilling to pay a premium for photomasks.

This trend prompted one expert to put a pressing item on his “wish list”—higher ASPs for masks. “If I was a mask maker, the first thing I would want is the ability to charge higher prices,” said , chief executive of D2S. “This is not only for leading-edge masks, but also for the high-volume nodes.

“Photomasks are fundamental to enabling , but they are too often perceived like a commodity,” Fujimura said. “If the semiconductor industry was willing to spend a little more on photomasks, not only would mask making be in great shape, but mask makers would be able to invest more in addressing many of the mask/litho process margin issues that plague wafer manufacturing yields. It would ultimately be a win-win for everybody.”

Other economic issues haunt the industry. At one time, there were dozens of leading-edge mask makers. But over time, many vendors couldn’t afford the soaring R&D costs at each node. As a result, the number of players dwindled. Today there are less than a dozen leading-edge mask makers, including both merchant and captive players. “Ten years ago, there were 120 reasonably good mask shops,” said Brian Grenon, director of sales and marketing for Rave, a mask repair tool maker. “Now, if you look at it, there are probably 15.”

This, in turn, presents some challenges for mask equipment vendors. Mask tool R&D costs have been escalating at advanced nodes. Yet there are fewer and fewer mask makers that can afford to buy these tools. “The cost of developing new equipment is very, very high,” Grenon said. “And the number of tools you sell is very low.”

Mask tool vendors, meanwhile, are willing to develop new systems, but they can no longer afford to foot the entire R&D bill. On the bright side, there are a growing number of examples where mask makers and IC vendors are willing to help fund the development of a given tool project.

And in one case, a chipmaker actually bought a mask equipment maker to help develop a critical tool technology. For example, Intel recently acquired IMS Nanofabrication, a developer of multi-beam mask writers.

Defect-free EUV mask blanks
On the technology side, meanwhile, mask makers want a number of new technologies. One technology, defect-free EUV mask blanks, is on the “wish list.”

The semiconductor manufacturing industry wants EUV lithography for good reason. Today, chipmakers will extend 193nm immersion lithography to 10nm and 7nm. This will also require a multiple patterning scheme, which increases mask complexity.

“We started to see the mask count at about 40 mask layers at 45nm/40nm,” said Kelvin Low, senior director of foundry marketing at Samsung. “That grew into 60 mask layers for the 14nm and 10nm node. If you push that without EUV, and stretch immersion into triple or quadruple patterning, we expect the mask count to go to about 80 to 85 at 7nm. In some cases, you could see 90 mask layers, depending on the area scaling that you are trying to target. We think maybe one or two companies can afford this technology. The masses probably cannot afford this technology.”

The solution, according to Low and others, is EUV. Based on 13.5nm wavelength technology, EUV promises to simplify the patterning flow, thereby reducing the mask count. But EUV is still not in production. There are persistent issues with the power source, resists and mask infrastructure.

On the mask infrastructure front, EUV mask blanks are critical. Basically, an optical mask blank consists of an opaque layer of chrome on a glass substrate. In contrast, an EUV mask blank consists of 40 to 50 alternating layers of silicon and molybdenum on a substrate. A number of absorbers are situated on this stack.

During the EUV mask blank production process, the substrates are inadvertently riddled with unwanted defects, such as pits and bumps. Over time, vendors have reduced the number of phase defects on EUV mask blanks to single digit numbers, compared to tens of thousands some five years ago.

Still, mask makers must find a way to prevent those unwanted defects from showing up on the photomask. Otherwise, the defect may get printed on the wafer.

To solve the problem, mask makers must locate the defect. Then, the defect is marked and covered by the absorber. In the flow, the e-beam patterns the mask, but it avoids the defect using pattern shifting techniques.

This technique works, but it’s complex and time consuming. And so the industry is still striving to get its hands on the EUV mask blanks with fewer defects, or preferably none.

“One area where work needs to be done is in evolving mask blank defects,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries.

“What we do need to see is a greater availability of low defect masks, if we are going to be able to apply EUV lithography to metal layers in high-volume manufacturing,” Levinson said. “This a very important point. There has been a massive investment in EUV lithography to date. If we are going to recover that investment, we cannot afford to have EUV lithography be a niche solution for contacts, vias and cuts.”

Multi-beam mask writers and new resists
Once the EUV- or optical-based mask blank is made, the next step is to pattern the blank. Traditionally, single-beam electron-beam tools are used to pattern or write the features on a photomask.

As the mask features become more complex, the e-beam takes a longer time to pattern or write a mask, thereby impacting photomask turnaround times and costs. On top of that, today’s single-beam e-beams have hit a physical limit in terms of current density.

The solution: Multi-beam mask writers. Using multiple beams in a single system, multi-beam mask writers promise to speed up the write times for both EUV and optical masks.

“We need multi-beam,” said Naoya Hayashi, research fellow at Dai Nippon Printing (DNP). “We need to solve the trade-off between resolution, accuracy and throughput.”

Today, there are two companies working on multi-beam mask writers—Intel/IMS and NuFlare. NuFlare recently disclosed the details of its multi-beam tool, which will ship in late 2017.

Screen Shot 2016-08-15 at 7.16.48 PM
Single-beam e-beam vs. multi-beam mask writer: Source: NuFlare

For some time, IMS has been developing a 50-keV mask writer with 262,144 programmable beams. “HVM tools are on track for 2016,” said Elmar Platzgummer, chief executive of IMS. “Starting in 2017, we will be able to offer our multi-beam mask writer solution, capable for the 7nm mask node, to the industry.”

The state of multi-beam mask writers is on the right track. “(IMS has) good technology and is a pioneer. But they are a small company. They needed resources to finalize the system. So, Intel decided to support them in order to commercialize their system. IMS won’t limit their activity only to Intel. Then, we have NuFlare, which is another competitor. Competition is very good for us,” DNP’s Hayashi said.

Meanwhile, as part of the patterning flow, the industry also wants new resists. “As line/space measurements fall below 50nm, the ability of each individual shape to print faithfully on the mask is impacted by its proximity to other shapes, making it more difficult to write these shapes accurately,” D2S’ Fujimura said.

“One way to address this accuracy problem is to use slower resists with less blur. However, slower resists increase mask write times,” Fujimura said. “Developing a mask resist that is both fast and accurate (for example, one that can resolve 15nm features at 80uC/cm2) would be a Holy Grail for mask making.”

Actinic inspection
While the outlook is bright for multi-beam mask writers, it’s a different story for another “wish list” technology—actinic-based inspection for EUV masks.

Today, traditional optical-based inspection tools are being used to find defects for both optical and EUV masks. E-beam inspection can also be used for EUV masks, but it’s slow in terms of throughputs.

But for future EUV masks, optical may run out of steam in terms of resolution, prompting the need for a technology called actinic inspection. Using the same 13.5nm wavelength as EUV, actinic inspection can supposedly find more defects than optical for EUV masks.

The problem is that no such tool exists. It would take several years and $500 million or more in funding to develop a production tool.

So for the foreseeable future, mask makers will generally use optical inspection for EUV masks. “(Optical inspection) is the technology available today,” said Mark Wylie, product marketing director at KLA-Tencor. “Obviously, companies like ourselves continue to investigate alternative solutions.”

Optical inspection is challenging for both EUV and optical masks. For EUV masks, the challenge is to find tiny and buried defects at 16nm and below.

There are also a multitude of inspection challenges for optical masks. For example, at 28nm (and above), optical masks tend to use rules-based optical proximity correction (OPC). On the mask, the features and shapes tend to be more simple and rectangular in nature.

At 10nm and 7nm, though, masks will use a combination of model-based OPC and inverse lithography technology (ILT). “We see an increase in the use of technologies, such as inverse lithography. This creates a kind of a curvilinear OPC feature and highly decorated primary features,” Wylie said. “You also have technologies like chromeless phase lithography or CPL. Before, you used to have nice and straight edges. Now, you fragment the edge to maintain the overlapping depth of focus.”

The use of more complex shapes and ILT-like features on the mask present some challenges for today’s inspection tools. “Suddenly, you might be inundated with millions of potential nuisance detections,” he said.

Looking to address the issues surrounding mask complexity, KLA-Tencor has rolled out two 193nm wavelength optical mask inspection systems for use at 10nm and 7nm.

The first system, the Teron 640, is geared for mask inspection in the photomask shop. The 640 features a dual inspection mode. For this, the tool first looks for defects. “We do a second pass using the scanner illumination conditions, and then we look at those defect locations. We try and figure out if they have any impact to the CD or edge placement error at the wafer scale,” Wylie said.

KLA-Tencor’s second tool, the SL655, is targeted for mask inspection in the fab. The SL655 performs several functions, such as incoming quality check and mask re-qualification. It features a new mode that enables the inspection of any mask type at high speeds.

These systems can handle both EUV and optical masks. “There are different challenges between them,” Wylie said. “The Teron platform is set up so that we can use transmitted and reflected light. For EUV, we have to use our reflective light channel. And then we have to use similar techniques that we use in our wafer inspection tools, with off-axis and optimized illumination conditions, to extract the defects.”

But will the industry ever develop actinic inspection?

The industry hasn’t given up on the idea. For example, Samsung has built its own, in-house actinic inspection tool for captive use. The system is a lab tool, not a production-worthy machine.

In addition, Japan’s Lasertec has developed an actinic-based inspection system for EUV mask blanks. The industry, according to sources, is exploring the idea of extending Lasertec’s actinic technology to pattern mask inspection for EUV masks. It’s unclear if or when that will happen.

Related Stories
Mask Maker Worries Grow Part 2
Executive Insight: Aki Fujimura
Multi-Beam Market Heats Up
Gaps Remain For EUV Masks


Ken Rygler says:

Mask makers have struggled to earn the cost of capital on an ongoing basis for decades. Mask making can be as capital intensive as IC manufacturing, but is not nearly as automated, and is saddled with higher labor costs. Mask makers never learned to price to value. The mask industry is similar to the personal computer industry: Intel and Microsoft (and now vertically integrated Apple) captured virtually all the profitability by virtue of monopoly positions, while PC producers were marginally profitable. In mask making, most of the value is captured by tool makers with virtual monopolies (NuFlare in writers, KLA-Tencor in inspection) and, for years, Hoya in blanks. Mask makers have campaigned for higher prices and financial support from customers, starting with Sematech some 20 years ago, with little to show for it. The more things change……..

Joe Silva says:

Why is 13.4nm or 13.5nm of special interest for EUV? Sure, that’s what you get from Sn sources, but even for Xe sources, this seems to be the target wavelength, even though Xe has better output at about 11nm. (Surely 11nm would be better for smaller feature sizes?)

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