Transistor Options Beyond 3nm

Complicated and expensive technologies are being planned all the way to 2030, but it’s not clear how far the scaling roadmap will really go.


Despite a slowdown in chip scaling amid soaring costs, the industry continues to search for a new transistor type 5 to 10 years out—particularly for the 2nm and 1nm nodes.

Specifically, the industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.

It’s hard to predict what will happen beyond 3nm. In fact, 3nm and beyond may never happen at all, as there are a multitude of unknowns and challenges in the arena. Perhaps chip scaling will finally run out of steam by then.

It’s even possible that today’s technology and its future iterations may provide enough performance beyond 5nm. Today’s leading-edge transistor type—the finFET—will likely extend to 5nm or 3nm, depending on how the nodes are defined. Then, at 4nm/3nm, some are moving toward a next-generation transistor technology called gate-all-around FETs, where a finFET is placed on its side and a gate is wrapped around it.

But there is also a chance the industry will require new and faster devices beyond gate-all-around. Many see a need to push the technology as far as possible, amid a revival in high-performance computing, artificial intelligence and machine learning. Autonomous driving, 5G, mobile and servers will also require more horsepower in the future. So in R&D, the industry is working on several technologies for 2.5nm and 1.5nm. At those nodes, the industry could go down the following paths:

  • Extend gate-all-around FETs or develop more complex versions of the technology, such as complementary FETs (CFETs) and vertical nanowire FETs.
  • Take existing finFETs and tweak them with new materials, creating what’s called a negative-capacitance FET (NC-FET).
  • Integrate devices into an advanced package.

Fig. 1: Next-gen transistor architectures. Source: Imec/ISS

There are other options as well, but it’s too early to predict a winner. “FinFETs have been a successful innovation. They still have at least one or two more generations. Beyond that, we have material changes-germanium or III-V channels. We may have gate-all-around. It’s still not clear exactly which of those ideas will eventually replace finFETs,” said Mark Bohr, senior fellow and director of process architecture and integration at Intel.

“Whether we are talking about negative-capacitance FETs, gate-all-around or III-V channels, you have to realize that modern logic products have a very demanding set of requirements,” Bohr said. “Getting high mobility is great, but you must also have low leakage. You must have low sub-threshold voltage and low power supply voltages. So right now, I’m not sure there is any technology that’s really been shown to be the winner across the board in terms of what today’s CMOS can do. We have other challenges to meet before we select a true winner.”

Why scale?
For years, the growth engine has revolved around Moore’s Law, the axiom that states transistor density would double every 18 months. Adhering to Moore’s Law, chipmakers introduced a new process every 18 months as a means to lower the cost per transistor.

Moore’s Law is viable, but it’s evolving. At each node, process cost and complexity are skyrocketing, so now the cadence for a fully scaled node has extended from 18 months to 2.5 years or longer. In addition, fewer foundry customers can afford to move to advanced nodes.

And not all are moving to leading-edge nodes. Demand for 28nm and above remains robust. And amazingly, 200mm fab demand remains strong. “We continue to see strong demand in 8-inch for 2018. And it’s coming from various applications. We see particularly strong demand in the mobile space for RF switches, the MCU, the embedded area, as well as the display area. The most challenging thing today is actually managing customers because the demand is overwhelming right now,” said Jason Wang, co-president of UMC, in a recent conference call.

Still, there are applications that require the latest processes, such as machine learning, servers and smartphones.

In another example, D2S sells a specialized high-end system based on graphics processors. The system is used for various semiconductor manufacturing applications. “So, we’re always at the very edge of utilizing available compute power,” said Aki Fujimura, chief executive of D2S. “I can say with great confidence that we’re not anywhere near about to run out of ways to use more computational power to improve semiconductor manufacturing. I’m sure that every other application domain for high-performance computing is in a similar situation. Particularly with deep learning taking off, I predict the thirst for more high-performance computing will continue to rise well beyond 7nm.”

Then there are applications that require both mature and advanced processes, such as automotive and certainly self-driving cars. “There are two different ecosystems. You have AI computations and then the sensors and controls that are in the vehicle,” said Ben Rathsack, senior member of the technical staff at TEL. “The demand for some of those older node technologies are actually increasing. And then, you have Nvidia’s processors. They may be doing AI processing. Of course, they are driving the high end.”

Meanwhile, the fab tools are ready for today’s devices. But for 2.5nm and 1.5nm, there are some gaps. To enable those nodes, the industry will require the following new technologies:

  • New lithography. Extreme ultraviolet (EUV) lithography is required for 7nm/5nm. Beyond 3nm, though, there may be a need for a next-generation EUV technology called high-numerical aperture (NA) EUV.
  • Selective processes. Chipmakers also a need a broader array of selective deposition and etch technologies, enabling vendors to deposit and remove materials in precise locations.
  • New interconnects schemes. The wiring schemes in chips are too congested, requiring new materials in the arena.

Then, at each node, the defects are becoming smaller and harder to find. “Lateral scaling, namely denser transistor layouts, drives the need to detect smaller defects and increases the need for design-aware inspection and review. Vertical scaling drives the need for detecting and verifying buried defects,” said Mark Shirey, vice president of marketing and applications at KLA-Tencor.

“Our problems are getting more difficult and they are more complicated. But one of the universals in this industry is that, when you have complexity and difficulty, that’s an opportunity,” said David Hemker, senior vice president and technical fellow at Lam Research, at a recent event.

Speaking on the general subject of Moore’s Law and other topics at the event, Hemker added: “We feel very bullish about being able to technically continue with Moore’s Law on almost any device. We see there are plenty of options as we want to go to 3nm and even below.”

Evolving the finFET
Today, meanwhile, chipmakers are ramping up 10nm/7nm finFETs. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Fig. 2: FinFET vs. planar. Source: Lam Research

After 7nm, the next technology nodes are 5nm, 3nm, 2.5nm and 1.5nm, according to the ITRS roadmap. The timing of these nodes is a moving target, however, and the node names are arbitrary and don’t reflect the specs of a transistor.

So how long will the finFET last? “We believe the finFET can last to about the 5nm node. It depends, of course, on how hard you scale the gate pitch. If you relax the gate pitch a little bit, the finFET is going to last longer,” said An Steegen, executive vice president of semiconductor technology and systems at Imec. “We see the nanosheet, the elongated nanowire, is a good candidate after that.”

For some, the successor to finFETs is a next-generation technology called the lateral gate-all-around FET. Slated for 4nm and/or 3nm in 2020 or so, gate-all-around is an evolutionary step from a finFET.

The two main types of gate-all-around FETs are the nanowire FET and nanosheet FET. In nanowire FETs, tiny wires are used for the channels. Nanosheet FETs use sheet-like materials for the channels.

Fig. 3: Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet. Source: IBM

Gate-all-around provides more control of the gate, which improves performance and reduces leakage. “It’s this improved gate control that enables you to continue to scale the gate length,” said Mike Chudzik, managing director of technical programs at Applied Materials.

It’s possible to develop gate-all-around devices using today’s fab tools and design techniques. For example, chipmakers could still leverage an established technique called design technology co-optimization.

The idea here is to reduce the track height and cell size in a standard cell layout at each node. Standard cells are pre-defined logic elements in a design. The cells are laid out in a grid. The track defines the height of a standard cell layout. For example, 7nm might have a 6-track height cell, enabling a device with a gate-pitch of 56nm and a metal pitch of 36nm, according to Imec.

Then, 4nm/3nm involves a layout with a 5.5-4.5 track height, enabling a device with a gate pitch from 36nm to 42nm, and a metal pitch from 21nm to 24nm, according to Imec.

Fig. 4: Cell library scaling enabled by scaling boosters. Source: Imec

Based on the roadmaps, the lateral nanowire/nanosheet FET may extend from 4nm/3nm to somewhere around 2nm, meaning the technology may last for only one or two nodes.

At 2nm, the industry faces some roadblocks. In theory, a 2nm device would consist of a 3-track height layout, but this type of scheme is difficult to envision, at least for now. “You really need at least 3 tracks in order to make a normal cell,” said Diederik Verkest, a program director at Imec. “With that type of architecture, it becomes extremely challenging.”

All told, the industry may need a new solution. But chipmakers don’t want to start from scratch. Instead, they prefer to take the existing work and manufacturing technologies and evolve them.

Fig. 5: Imec’s view of transistor roadmap.

Imec proposes two options—CFETs and vertical nanowires. Slated for 2.5nm and beyond, a CFET is a more complex version of a gate-all-around device. Traditional gate-all-around FETs stack several p-type wires on top of each other. In a separate device, the transistor stacks n-type wires on each other.

In CFETs, the idea is to stack both nFET and pFET wires on each other. A CFET could stack one nFET on top of a pFET wire, or two nFETs on top of two pFET wires.

Since a CFET stacks both n- and p-type devices on each other, the transistor provides some benefits. “The main benefit is area. Area scaling brings you some benefits in power and performance,” Verkest said. “In terms of electrostatic control, a CFET would be the same as normal nanowire. They are both gate-all-around architectures.”

Other benefits are less clear. CFETs would provide an area scaling boost, but they have roughly the same transistor specs as a traditional gate-all-around device.

CFETs are more difficult to make in the fab and may require a taller structure. That, in turn, may mean higher capacitance.

Another solution is a vertical nanowire FET (VFET). A lateral gate-all-around FET stacks the wires horizontally. In contrast, VFETs stack the wires vertically. The source, gate and drain are stacked on top of each other. That means there is a gain in area.

Fig. 6: Lateral nanowire FET vs. vertical nanowire. FET Source: Imec

VFETs have some drawbacks. The VFET is an effective device to scale SRAM. But it is not a device that scales the logic cell.

VFETs are also difficult to make in the fab, but the technology has been demonstrated in the lab. At IEDM, Imec, Lam Research and KU Leuven presented a paper on the VFET with vertical nanosheets and III-V materials. In the flow, a pattern is formed on a structure using e-beam lithography. The surface is etched, forming vertical nanowires ranging from 25nm to 75nm in diameter in arrays from 1 to 100 nanowires, according to the paper.

What are NC-FETs?
There are other options. In 2008, researchers from Purdue University proposed the idea of so-called negative-capacitance FETs or NC-FETs.

Targeted for 3nm and beyond, the NC-FET isn’t a new device. Instead, an NC-FET takes an existing transistor with a high-k/metal-gate stack based on hafnium oxide. Then, the gate stack is modified with ferroelectric properties, creating a steep sub-threshold slope device well below the 60mV/decade limit.

Fig. 7: Negative capacitance FET. Source: Peter Grünberg Institute for Semiconductor Nanolelectronics

Planar devices, finFETs and even gate-all-around, can be modified with ferroelectric properties, as long as it incorporates hafnium oxide. “Essentially, a ferroelectric is like a voltage amplifier. You put one voltage on it. Because the way it interacts, it amplifies the voltage. That’s why you get this enhanced sub-threshold slope,” Applied’s Chudzik said.

Fig, 8: Schematics of NC-FET. Source: SRC, University of Nebraska-Lincoln

NC-FETs fall in the same category as tunnel FETs (TFETs), a futuristic steep sub-threshold transistor candidate. Unlike NC-FETs, though, TFETs would require a completely new structure.

NC-FETs are related to a technology called the ferroelectric FET (FeFET). Both NC-FETs and FeFETs harness the ferroelectric properties in hafnium oxide.

FeFETs and NC-FETs are different. “The most important difference is that the NC-FET is for logic and the FeFET is for memory. The NC-FET, in principle, is a logic device that does not have a nonvolatile memory. The other one, the FeFET, is a memory device that is nonvolatile,” said Stefan Müller, chief executive of Ferroelectric Memory Co. (FMC), a startup that is developing FeFETs.

In both cases, a ferroelectric material is sandwiched between two other materials and deposited into a hafnium-based gate stack using deposition. “In FeFETs, the desire is to keep this buffer between the ferroelectric and silicon bulk material as thin as possible. This has to do with data retention. The thinner the buffer layer, the better the data retention,” Müller said. “NC-FET is different. The NC-FET transistor, in principal, has no data retention. That means the requirement on this buffer layer between the ferroelectric and silicon bulk is different.”

In one example, GlobalFoundries recently presented a paper on an experimental 14nm finFET, which incorporates doped hafnia ferroelectric layers in the gate stack. GlobalFoundries called it a 14nm ferroelectric finFET. It could be classified as finFET with negative-capacitance or an NC-FET.

In a 14nm finFET, GlobalFoundries tested ferroelectric layers at thicknesses of 3nm, 5nm and 8nm. They also tested a 1.5nm undoped layer. “We find that an 8nm thick film still yields functional devices,” said Zoran Krivokapic, a senior member of the technical staff at GlobalFoundries, in the paper. “Ferroelectric devices show improved sub-threshold slopes as low as 54mV/dec. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved sub-threshold slope reduces their active power.”

NC-FETs face some challenges, though. “There is a lot of promise and interest in it, but there are a lot of unanswered questions. With the gate, you have only so much volume in which to put a ferroelectric material in. The ferroelectrics are thick, 50 to 80 angstroms. That would close the gap on a modern finFET,” Applied’s Chudzik said. “The industry is already at 7nm, so they need to scale that material and still show it’s a ferroelectric. Reliability is a challenge. And then there might be some unique device design constraints due to some parasitics.”

Other solutions
IC makers are also looking for an alternative from chip scaling. One idea is to put multiple devices in an advanced package, which may provide the same functionality as a scaled device at a lower cost.

Some call this hybrid scaling or heterogeneous integration. “I don’t think people will say, ‘And now we are going to stop with device scaling and we are going to switch to hybrid scaling,'” Imec’s Steegen said. “Think about packages today and the way you stack different dies in a package. You could also see this already as a form of hybrid scaling. You could say it has started today. But we can continue to build on that road.”

What’s next? Beyond 1.5nm, the roadmap is cloudy. On Imec’s roadmap, there are several futuristic technologies, such as TFETs and spin-wave devices. 3D nanofabrics, a logic version of 3D NAND, is also a possibility.

These futuristic devices will require new tools and materials, not to mention funding.

Clearly, there are more questions than answers beyond 5nm. Perhaps gate-all-around is the answer, or researchers will stumble upon a new technology. Then, of course, today’s technology could last longer, pushing out the need for these newfangled transistors.

Related Stories
The Race To 10/7nm
What’s After FinFETs?
What’s Next For Transistors
New BEOL/MOL Breakthroughs?
Variation Spreads At 10/7nm
Looming Issues And Tradeoffs For EUV
Extending EUV Beyond 3nm
Multi-Patterning Issues At 7nm, 5nm
Inside Advanced Patterning
What’s Next For Atomic Layer Etch?


Santosh Kurinec says:

Very nice article! I am going to share with my students of Microelectronic Engineering. We are working on some of these novel ideas.

Kushal Shah says:

Well written article.

Venkatesh says:

Good article

Bill Pohlman says:

It is interesting that no one seems to be looking at the future of digital noise that these exotic transistors create when switching. The total current do to switching goes to many 100s of amps.

Parviz Ghazavi says:

Well written, a good summary for next generation transistors, beyond 5nm.

Mark says:

It would be interesting to see some transistor drawings that show individual atoms. After all, the raw silicon lattice spacing is 5.43 Angstroms. So 3nm doesn’t give you many atoms to work with.

Sreedhar says:

Wonderful artical about semiconductor industry

N7 says:

The 7nm patterning seems already defined by TSMC and GlobalFoundries.

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