What’s After FinFETs?

Chipmakers exploring nanosheet, nanoslab, nano-ring and hexagonal FETs.

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Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it’s still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next.

The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process complexities and costs escalate at each node. As a result, fewer customers can afford to design chips around advanced nodes.

In theory, finFETs are expected to scale to 5nm as defined by Intel. (A fully-scaled 5nm process is roughly equivalent to 3nm from the foundries). Regardless of the confusing node names, the finFET likely will run out of steam when the fin width reaches 5nm. So at 5nm or beyond, chipmakers will need a new solution. Otherwise, traditional chip scaling will slow down or stop completely.

For some time, chipmakers have been exploring various transistor options for 5nm and beyond. So far, only Samsung has provided details. In May the company rolled out its technology roadmap, which includes a nanosheet FET for 4nm by 2020.

Other chipmakers also are leaning toward similar structures in the same timeframe, even though they have not publicly announced their intentions. Nanosheet FETs and another variant, nanowire FETs, fall into the gate-all-around category. Other variants include hexagonal FETs, nano-ring FETs and nanoslab FETs.


Fig. 1: Types of horizontal gate-all-around architectures. Source: Qualcomm, Synopsys, Applied Materials

For now, gate-all-around technology appears to be the most practical technology after finFETs. It’s an evolutionary step from finFETs and shares many of the same process steps and tools. A lateral gate-all-around technology is basically a finFET on its side with a gate wrapped around it. Tiny wires or sheets serve as the channels.

There are other transistor options, as well. Some chipmakers are even looking at ways to scale using advanced packaging. Vendors are weighing the options and looking at the technical and economic merits of each. “The finFET can scale one or two generations,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel. “But the question might be, ‘Is one of the alternates a better option, whether it’s gate-all-around, III-V materials or tunnel FETs?’ If we had to, we could scale finFETs. But the question is, ‘Is there a better option?’”

By III-V, Bohr is referring to a finFET with III-V materials in the channels, which can boost the mobility in devices. A tunnel FET (TFET) is a steep sub-threshold slope device that operates at low voltages.

While gate-all-around technology is gaining steam, it isn’t the consensus pick—yet. “I won’t necessarily say that, but it’s certainly getting a lot of attention,” Bohr said in an interview. “It’s too early to predict which ones will be successful. But there are enough good ideas to ensure there will be a couple more generations.”

Analysts, however, believe that 10nm/7nm finFETs will last for the foreseeable future. “(FinFETs provide a) combination of higher performance, lower power consumption and lower cost,” said Handel Jones, chief executive of International Business Strategies (IBS).

If next-generation transistors go into production at 5nm or beyond, the technology will be expensive and limited to specific apps. “Gate-all-around is likely to be adopted, but the major benefits will be high performance,” Jones said. At 5nm, it will cost $476 million to design a mainstream chip, compared to $349.2 million for 7nm and $62.9 million for 28nm, according to IBS.


Fig. 2: IC design costs. Source: IBS

To help customers get ahead of the curve, Semiconductor Engineering has taken a look at what’s ahead and highlighted the difficult process steps.

Different options
There are at least three main paths forward—brute-force scaling, staying at mature nodes, and advanced packaging.

Those with deep pockets likely will continue down the traditional scaling path at 10nm/7nm and beyond. Gate-all-around is the leading contender beyond finFETs, at least for now. Longer term, there are other options, such as III-V finFETs, complementary FETs (CFETs), TFETs and vertical nanowires. Vertical nanowires involve stacking wires vertically.

A CFET is a more complex gate-all-around technology, where you are stacking nFET and pFET wires on top of each other. The current gate-all-around devices stack one type of wire, whether its nFET or pFET, on each other.

CFETs, TFETs and vertical nanowires are more revolutionary technologies and not expected in the short term. They will require new breakthroughs.


Fig. 3: Next-gen transistor architectures. Source: Imec/ISS.

So how will the high end play out? “7nm will be a long-lived node,” said Gary Patton, chief technology officer at GlobalFoundries. “FinFETs will have a lot of legs. There is still a lot of room to extend finFETs.”

After finFETs, there are several options in R&D. For example, GlobalFoundries is exploring nanosheets, nanowires and vertical nanowires.

The decision and timing to go with one technology over another depends on technical and economic factors. “You are trying to develop a process that is manufacturable and delivers a value proposition,” Patton said. “This stuff is not as straightforward as it used to be. There is a lot more vetting required.”

In fact, a given technology might be in R&D for a decade. Then, based on a set of criteria, the best technologies appear in the market. Many others fall by the wayside when that happens.

To be sure, though, not all companies will require finFETs and nanowires. Most will stay with 22nm planar processes and above. Many can’t afford finFETs, and it’s not required for analog, RF and other devices.

“10nm, 7nm and 5nm sound attractive,” said Walter Ng, vice president of business management at UMC. “But how many can really afford it and justify the design and manufacturing expense? The demand pushing the bleeding-edge is really for a select few.”

But even those at 22nm and above face some challenges. “Everybody else needs to look at how they can continue to compete,” Ng said. “They are trying to find a way to differentiate and squeeze out costs.”

That’s why many are drawn towards advanced packaging. All chips require an IC package. For example, customers can use traditional packages, such as flip-chip BGA. Advanced packaging extends that idea, integrating multiple die in the same package to create a high-performance system. 2.5D/3D and fan-outs are examples of this approach.

So what’s the ultimate winner in the market? “There’s not one answer,” said David Fried, chief technology officer at Coventor. “People are really looking for the application to drive the physical solution.”

Fried pointed out that there is no one-size-fits-all solution. For example, finFETs or follow-on transistors make sense for high-end microprocessors. “But for IoT devices, that may be an incorrect direction,” he said. “There is no one application that is driving the entire market. People have to stop searching for one answer that fits everything. A lot of different things can win all at the same time, but it’s going to be for different applications.”

Meanwhile, looking into his crystal ball, Fried said: “My suspicion is that 7nm looks pretty evolutionary. It will be finFET. If we see a change beyond finFET, it could be at 5nm. But remember, a lateral gate-all-around nanowire device is like a finFET with two extra etches. Going from a finFET to a lateral gate-all-around nanowire device is pretty evolutionary. I hope we start seeing that at 5nm. Beyond that, we don’t have much visibility.”

Transistor trends and processes
Today, meanwhile, the finFET is the leading-edge transistor. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

A key spec is the gate-pitch. The gate-pitch for Intel’s 10nm finFET technology is 54nm, compared to 70nm for 14nm. (Intel’s 10nm is the equivalent to 7nm from the foundries.)

The big decision comes when the gate-pitch approaches 40nm. Based on simulations from Imec, the finFET begins to teeter at a 42nm gate-pitch. “The nanowire will scale below that and still have good electrostatic control,” said An Steegen, executive vice president of semiconductor technology and systems at Imec. The nanowire FET, according to Imec, has demonstrated good electrostatic control at a 36nm gate pitch. Imec has also devised a nanowire down to 9nm in diameter.


Fig. 4: Imec’s tiny nanowire. Source: Imec

In general, gate-all-around provides a performance boost over finFETs, but there are several challenges, namely drive current and parasitic capacitance. Compounding the issues is a relativity new layer called the middle-of-line (MOL). The MOL connects the separate transistor and interconnect pieces using a series of contact structures. In the MOL, parasitic capacitance is problematic. It creates external resistance in various parts of the device. This includes the contact to the junction, where the low-resistance Schottky barrier and the silicide resides.

One version, a lateral nanowire FET, is where you take a finFET and chop it into pieces. Each piece becomes a tiny horizontal nanowire, which serves as the channel between a source and drain.

Nanosheet or nanoslab FETs are the other common variants. Both technologies resemble a lateral nanowire FET, but the wires are much wider and thicker.

Each version has some tradesoffs. “(The nanosheet FET) is not quite as revolutionary as they might want it to sound,” Intel’s Bohr said. “It’s just finFETs laid on their sides. Not sure if the value is quite as strong as nanowires.”

In nanowire FETs, the gate surrounds the entire wire, enabling more control of the gate. “It’s this improved gate control that enables you to continue to scale the gate length,” said Mike Chudzik, senior director of the Transistor and Interconnect Group at Applied Materials.

As stated above, a finFET is cut into pieces. As a result, the amount of surface area on the device decreases. “You are losing that real estate of silicon,” Chudzik said. “I’m sure you are gaining in off-current, but you are losing in overall drive current.”

That’s why a nanosheet FET makes sense. “That’s where you start to elongate these wires,” he explained. “You are gaining in volume for your drive current. In addition, you can also play tricks with the shapes of these wires or sheets to help reduce the capacitance.”

Another version, the nano-ring FET, has a similar benefit. “The whole idea of the nano-ring is to actually squeeze the sheets together a little bit,” he said. “What that does is effectively reduce the capacitance.”

The first gate-all-around devices will likely have three wires. Over time, though, chipmakers will need to stack more wires on top of each other to provide more performance. “We certainly don’t want to introduce new device architectures that last only a node. (So the idea) is to consider stacking more nanoslabs on top of each other,” he said. “But you can’t just keep infinitely stacking channels, because you get a lot of the same parasitic, capacitance and resistance problems as you do with taller finFETs.”

In a sign of things to come, GlobalFoundries, IBM and Samsung recently presented a paper on a nanosheet FET for 5nm and 3nm. The technology is said to show better performance with a smaller footprint than finFETs.


Fig. 5: Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet. Source: IBM.

Using extreme ultraviolet (EUV) lithography for some layers, the nanosheet FET from the three companies has three sheets or wires. It has a gate length of 12nm and a 44nm/48nm contacted poly pitch with 5nm silicon channels. The nFET has a sub-threshold slope of 75mV/decade, while the pFET is 85mV/decade, according to the paper.

In the lab, researchers stacked nanosheets with three layers of 5nm sheet thickness and a 10nm space between them. They demonstrated inverter and SRAM layouts using single stack nanosheet structures with sheet widths from 15nm to 45nm. “It has superior electrostatics and dynamic performance compared to extremely scaled finFETs with multiple threshold and isolation solutions inherited from finFET technologies. All these advantages make stacked nanosheet devices an attractive solution as a replacement of finFETs, scalable to the 5nm device node and beyond, and with less complexity in the patterning strategy,” according to the paper.


Fig. 6: Stacked nanosheet process sequence and TEM. Source: IBM, Samsung, GlobalFoundries.

Generally, the process steps are similar between gate-all-around and finFETs, with some exceptions. Making a gate-all-around is challenging, however. Patterning, defect control and variability are just some of the issues.

The first step in gate-all-around differs from a finFET. In gate-all-around, the goal is to make a super-lattice structure on a substrate using an epitaxial reactor. The super-lattice consists of alternating layers of silicon-germanium (SiGe) and silicon. Ideally, a stack would consist of three layers of SiGe and three layers of silicon.

Then, like a finFET flow, the next step involves the formation of the shallow trench isolation structure. “It’s critical that the super-lattice has ultra-abrupt junctions between silicon germanium and silicon,” Applied’s Chudzik said.

Here comes the next critical step. In gate-all-around, the gate not only wraps around the channel, but it will wrap around some of the contact area. This adds capacitance to the mix. “So you need to form what’s called an inner spacer, where you actually separate the high-k from the source-drain region. That can be done with an ALD-type film,” Chudzik said.

Then, using a replacement process, the SiGe layers are removed in the super-lattice structure. This, in turn, leaves the silicon layers with a space between them. Each silicon layer forms the basis of a nanowire.

Finally, high-k/metal-gate materials are deposited, thereby forming a gate. In effect, the gate surrounds each of the nanowires.

Mask/litho challenges
Along the way, there are also a series of lithography steps. At 16nm/14nm and 10nm/7nm, chipmakers are using today’s 193nm immersion lithography tools and multiple patterning.

At 7nm and/or 5nm, the industry hopes to insert EUV. In EUV, a power source converts plasma into light at 13.5nm wavelengths, enabling finer features on a chip.

Chipmakers hope to insert EUV for the most difficult parts, namely metal1 and vias. They will continue to use traditional lithography for many other steps.

EUV can reduce the cost per layer by 9% for the metal lines and 28% for vias, compared to triple patterning, according to ASML. “(EUV) eliminates steps in the fab,” said Michael Lercel, director of product marketing at ASML. “If you look at the cost of doing multiple immersion lithography steps, coupled with the other process steps, such as cleaning and metrology, we believe that EUV is less costly per layer versus triple patterning immersion and certainly quadruple patterning and beyond.”

EUV isn’t ready for production, however. ASML is readying its latest EUV scanner—the NXE:3400B. Initially, the tool will ship with a 140-watt source, enabling a throughput of 100 wafers per hour (wph).

To put EUV in production, chipmakers want 250 watts, enabling 125 wph. Recently, though, ASML has developed a 250-watt source, which will be shipped early next year.

EUV resists, meanwhile, are another stumbling block. To reach the desired throughput for EUV, the industry wants EUV resists at a dose of 20mJ/cm². “Good imaging seems to be more towards the 30mJ/cm² to 40mJ/cm² range today,” said Richard Wise, technical managing director at Lam Research. “So the dose is not necessarily where we would like it to be.”

With a 30mJ/cm² dose, for example, an EUV scanner with a 250-watt source produces 90 wph, which is below the desired 125 wph target, according to analysts.

But developing resists at the desired dose is challenging. “There are a lot of fundamental physical challenges to lower that dose because of the stochastic effects in EUV,” Wise said.

This involves a phenomenon called photon shot noise. A photon is a fundamental particle of light. Variations in the number of photons can impact EUV resists during the patterning process. It can cause unwanted line-edge roughness (LER), which is defined as a deviation of a feature edge from an ideal shape.

While the industry is wrestling with the resists, photomask makers are developing EUV masks. Today’s optical mask consists of an opaque layer of chrome on a glass substrate. In contrast, an EUV mask is a reflective technology, which consists of alternating layers of silicon and molybdenum on a substrate.

“We need EUV in order to avoid triple patterning,” said Aki Fujimura, chief executive of D2S. “This means that EUV masks will have a lot more main features than ArF masks, and that each of these features will be small. Since EUV more accurately reflects mask aberrations on the wafer, EUV masks need to print more of the smaller things and each more accurately.”

To make EUV masks, photomask manufacturers will require some new tools. For example, they want faster e-beam mask writers. As mask features become more complex, today’s single-beam e-beam tools take a longer time to pattern or write a mask. Today’s e-beams are based on variable shape beam (VSB) technology.

The solution is multi-beam mask writers. Today, IMS is shipping a multi-beam mask writer for both optical and EUV masks, while NuFlare is also developing multi-beam tools.

Multi-beam will help with mask yields, turnaround times and cost. “Most masks in the world will still be perfectly fine with VSB writers,” Fujimura said. “But the critical few will need multi-beam writing to keep the write times reasonable.

“In the most likely scenario that EUV is ready for 5nm, the demand for multi-beam writing will be high for some mask layers. For example, if a mask layer contains a large number of non-orthogonal, non-45-degree features, multi-beam will be required for sure. 193i is blind to small perturbations on the mask, so ‘Manhattanization’ of those patterns work fine with relatively large stepping sizes,” he said. “However, EUV can see much better, and that will hugely increase the shot count, making VSB writing unlikely. But these are very specialized masks for specialized chips. For the majority of mask layers, even though the number of main features on the mask will explode by factors, the number of shots needed to shoot the decorations and SRAFs will decrease substantially. An advanced VSB writer with sufficient precision may be fine for a majority of EUV masks.”

Inspection/metrology challenges
Inspection and metrology are also critical at 5nm and beyond. “The trend toward vertical architectures introduces the challenge of buried defects for inspection and complex profiles for metrology,” said Neeraj Khanna, senior director of customer engagement at KLA-Tencor. “EUV will experience high-volume adoption at these nodes, driving new random and systematic defect mechanisms. Stochastic issues will drive a need for higher sampling.”

What does this all mean? “We expect these new architectures to drive new sets of requirements for metrology and inspection,” Khanna said. “The industry has to continue to innovate and extend core technologies.”

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  • Teemu Soilamo

    An excellent and very understandable overview for a semiconductor dilettante like myself!