Device Characteristics of GAA-Structured CMOS and CTFET Under Varying Temperatures


A new technical paper titled "Vertical-Stack Nanowire Structure of MOS Inverter and TFET Inverter in Low-temperature Application" was published by researchers at National Tsing Hua University and National United University in Taiwan. Abstract "Tunneling field effect transistors (TFET) have emerged as promising candidates for integrated circuits beyond conventional metal oxide semiconductor ... » read more

Research Bits: September 11


Combining digital and analog Researchers from École Polytechnique Fédérale de Lausanne (EPFL) propose integrating 2D semiconductors with ferroelectric materials for joint digital and analog information processing, which could improve energy efficiency and support new functionality. The device uses a 2D negative-capacitance tungsten diselenide/tin diselenide tunnel FET (TFET), which consu... » read more

What’s A Mott FET?


The unique physics of two-dimensional semiconductors offers the potential for new kinds of switches that could extend the usefulness of conventional MOSFETs into a variety of new areas. A MOSFET applies a voltage to one side of the gate capacitor. The resulting electric field in the channel shifts the band structure and facilitates or impedes the flow of carriers. So as devices shrink, the g... » read more

New Patterning Options Emerging


Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

What’s After FinFETs?


Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

TFETs Cut Sub-Threshold Swing


One of the main obstacles to continued transistor scaling is power consumption. As gate length decreases, the sub-threshold swing (SS) — the gate voltage required to change the drain current by one order of magnitude — increases. As Qin Zhang, Wei Zhao, and Alan Seabaugh of Notre Dame explained in 2006, SS faces a theoretical minimum of 60 mV/decade at room temperature in conventional MO... » read more

What’s Next For Transistors


The IC industry is moving in several different directions at once. The largest chipmakers continue to march down process nodes with chip scaling, while others are moving towards various advanced packaging schemes. On top of that, post-CMOS devices, neuromorphic chips and quantum computing are all in the works. Semiconductor Engineering sat down to discuss these technologies with Marie Semeri... » read more

Power/Performance Bits: May 31


Solar thermophotovoltaics A team of MIT researchers demonstrated a device based on a method that enables solar cells to break through a theoretically predicted ceiling on how much sunlight they can convert into electricity. Since 1961 it has been known that there is an absolute theoretical limit, called the Shockley-Queisser Limit, to how efficient traditional solar cells can be in their ... » read more

Manufacturing Bits: Dec. 30


Mechanical switches For years, the industry has been talking about the use of advanced mechanical switches in low-power applications. In theory, mechanical switches have zero off-state leakages, abrupt ON/OFF switching capabilities and small voltage swings. Mechanical switches could overcome the energy efficiency limit of CMOS. In fact, mechanical switches could replace CMOS in some applica... » read more

Unraveling The Mysteries At IEDM


In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

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