What’s Next In Scaling, Stacking

The 40nm gate-pitch cliff, 3D SoCs with microfluidic cooling, new fan-outs and 2.5D—it’s all on the table.


An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation.

SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies either ramping or just around the corner. These processes are based on finFET transistors, where the control of the current is accomplished by implementing a gate on each of the three sides of a fin. How long will the finFET last?

Steegen: From Imec’s perspective and the analysis that we’ve done, the finFET is a strong device. We see this one lasting. Let’s use gate pitch, because that is actually where you see a little bit of a cliff between a fin verses a nanowire. This is around 40nm. So, you could say if 5nm still parks itself in a 40nm gate pitch range, it’s there we believe that a finFET is still a very strong device.

SE: Is this the “foundry 5nm” node? (In the process technology world, the “foundry 5nm” or “industry 5nm” node is roughly equivalent to a full-scaled 7nm technology from IDMs like Intel and R&D organizations such as Imec. So, a “foundry 3nm” may resemble a full-scaled 5nm node from Intel and Imec.)

Steegen: Let’s set the record straight. When you are talking about 5nm, you are probably talking about the industry’s 5nm and not Imec’s. Internally, Imec has a node nomenclature. We have to set this straight, because Imec does full-node scaling.

SE: Regardless of the node numbers, what’s after the finFET? Many are talking about nanowire FETs. (A nanowire FET, sometimes referred to as a gate-all-around FET, is a finFET turned on its side with a gate wrapped around it.)

Steegen: When you say 5nm, that’s definitely a fin, because the gate pitch is still above 40nm. But at 3nm, this 40nm gate pitch could be the cliff, and where the nanowire will be able to re-enable gate-pitch scaling. It’s important that we pin it on gate pitch. It’s still unclear what the industry is going to do on scaling and how fast and how aggressively it will scale. But from the simulations that we’ve run, it’s around that 40nm gate pitch. This is where the nanowire will scale below that and still have good electrostatic control. This is where the fin starts to get shaky. That comes along with a gate length, I would say, between 10nm and 12nm.

SE: So what are the transistor candidates at 5nm and 3nm?

Steegen: At 5nm, we actually only have finFETs. At 3nm, that’s around a 42nm to 36nm gate pitch. There, we see that a nanowire is at the same performance as a fin. But a fin is at a 42nm gate pitch and a nanowire is at 36nm. So you scale better with a nanowire. That’s basically the translation.

Fig. 1: Next-gen transistor architectures. Source: Imec/ISS.

SE: A nanowire FET is basically an evolutionary technology from a finFET, right?

Steegen: A nanowire is a derivative of a finFET. There are some process modifications you actually do in the fin module.

SE: Besides scaling, you also talk about another technology on the roadmap called hybrid scaling. Can you elaborate on that?

Steegen: There are many names for it. We call it hybrid scaling. Some call it heterogeneous scaling or integration. For us, it’s a collective name of when you start partitioning an SoC into particular subsystem blocks. And then you say, ‘I would like to use the preferred technology for each block and then find a way to integrate this together.’ It can be next to each other or on top of each other. So you can stack them on top of each other. When does that come in? Again, I don’t want to pin a time for that. It depends on the complexity of what you want to co-integrate together. You need to weigh the complexity and the cost adder of doing that co-integration. It also depends on the readiness of the new elements. Overall, the cost picture must come together.

Fig. 2: Conventional SoC. (Source: Imec)

SE: Will hybrid scaling or heterogeneous integration displace traditional chip scaling?

Steegen: I don’t think people will say: ‘And now we are going to stop with device scaling and we are going to switch to hybrid scaling.’ You are going to see this coming in. Think about packages today and the way you stack different dies in a package. You could also see this already as a form of hybrid scaling. You could say it has started today. But we can continue to build on that road.

SE: In hybrid scaling, an SoC has various blocks. What will a chip look like for this technology?

Steegen: It’s depends on your application. Typically, you might have a CPU, GPU, cache memory, I/Os and analog. Of course, a server chip looks different than a mobile chip. If you have many cores, how much cache do you need? If you have a large L3 cache on that die, that probably makes a lot of sense to put that on top. If you have a small amount of cache, that could be a different story.

Fig. 3: Hybrid design. (Source: Imec)

SE: In a presentation, you said hybrid scaling is moving in two directions. In an SoC, the sub-system blocks could sit next to each other in a 2D configuration. Then, you could also stack various blocks in a 3D configuration. How would you stack them?

Steegen: In 3D, you prefabricate the parts. Then you stack them, typically face-to-face, on top of each other. And you need alignment accuracy. Let’s say, for instance, I stack an I/O on top of my CPU. We typically say you need about 2µm or below alignment accuracy with stacking. Wafer-to-wafer bonding is definitely a way to go there.

SE: Imec and EV Group are working on a next-generation wafer-to-wafer bonding technology and have demonstrated a 1.8µm pitch overlay accuracy. In this process, the top and bottom wafers are aligned and then bonded, creating a stacked IC. This is used for  today with 3D chip stacking in development. For 3D chip integration, though, the alignment accuracy must be improved by 5 to 10 times versus a MEMS process. That’s one of the challenges, right?

Steegen: That’s why the wafer-to-wafer bonding technique needs to be aligned at 2µm or below.

SE: Besides wafer-to-wafer bonding, the industry is working on other forms of stacking. For example, there is monolithic 3D integration or sequential technology. This is where you stack transistors, right?

Steegen: This is where you have one layer, you build your devices, and then you actually start with a second layer of devices. You pattern those and then connect them. Your thermal budget is extremely important there. If you have metal on the first device, your thermal budget for that second device is very limited.

SE: Imec is working on this using a layer transfer technique. How does that work?

Steegen: We call it sequential. The way we do it is you form your first device and pattern it. Then, let’s say you finish your contacts or sometimes your metal. And then, depending on what that second device will be, you basically add layers. The first is a buffer layer. But you basically layer transfer the layers in. There are other approaches out there.

SE: How does sequential technology compare with the wafer-to-wafer bonding approach?

Steegen: There, of course, you can go to much finer alignments than with die stacking. With wafer-to-wafer bonding, you are limited to 2µm or below. With sequential, you can go to 100nm or below.

SE: What are some of the things you can do with sequential technology?

Steegen: One of the ideas that we have, which looks promising, is with high-speed analog devices. How do you integrate those as closely as possible with CMOS? One way could be by layer transfer and putting them on top. In addition, you could also layer transfer III-V materials. III-V materials, as you know, provide high performance. That might be of interest, but we are still evaluating that.

SE: What about more traditional forms of IC packaging? Where is that going?

Steegen: I’ve described hybrid scaling. That is where you start to partition an SoC and get the parts on top of each other with a wafer-to-wafer bonding stacking technique. Then, when you look at packaging today, it involves packaged dies. At this moment, it’s die level. And with that, you try to package this as compact as possible in a wafer-level package.

SE: Isn’t Imec working on fan-outs?

Steegen: This involves a next-generation technology we are working on. It’s like a mold and you embed your pre-fabricated dies in the most compact way. To enable that, you need TSVs and micro bumps. You need to get them as dense as possible. Of course, you need to improve on the density in that fan-out wafer-level package. In that sense, we also consider this as one way of 3D stacking, but it’s a completely different way than wafer-to-wafer bonding for an SoC.

SE: What do you envision for fan-out?

Steegen: If you look Imec’s roadmap today in 3D and stacking, you have packaging where we are moving to this fan-out wafer-level packaging. It also includes Wide I/O. It also involves memory cubes.

SE: So Imec sees Wide I/O moving into a fan-out package?

Steegen: That is maybe a longer-term approach. It comes down to scaling the bumps.

Fig. 4: 3D-SoC functional scaling. (Source: Imec)

SE: What happened to 2.5D?

Steegen: There are a few products out there on interposers today. We continue to work on that. We are trying to get more functions embedded in that interposer.

SE: What are the general challenges with stacked die?

Steegen: It’s across the board there. Look at 3D thermal heat management. For years, Imec has worked on thermal models in terms of coming up with different solutions to dissipate the heat. We are even working on microfluidics today to cool down the stack dies. This is an item that needs to be solved. We also need EDA tools to basically enable good scaling and routing when it comes to stacking. Then, there’s the power delivery network. Indeed, we need to make sure that you have your power delivery in the most energy efficient way for all of the stacked dies.

SE: Finally, let’s briefly talk about silicon photonics. What’s happening there?

Steegen: We have advanced silicon photonics platforms at Imec, where we work on each of the individual optical components like next-generation detectors, modulators and waveguides. We bring these together in demonstration vehicles. There are two prototypes, where we basically have an advanced CMOS host IC that we attach to our silicon photonics chip. Today, we are already doing this demonstration on 14nm.

SE: What else?

Steegen: Today, data centers have an aggregate bandwidth of 3.2 terabits-per-second. They need more bandwidth for every generation. So what is the performance of the optical components that you need to get? Of course, the higher performance you get from those components, the less multiplexing and multi-lanes you are going to need. We have demonstrated direct detection and modulation at 100 gigabits-per-second with individual components working at about 50 GHz today. You get more performance on one channel. This is for data centers. So, we are talking about five meters or more. Then, the optical module is still a separate module on the PCB. But the long-term vision is to bring that closer towards the package so we can then start thinking about optical links chip-to-chip in the package. That’s further out.

Related Stories
Uncertainty Grows For 5nm, 3nm
Nanosheets and nanowire FETs under development, but costs are skyrocketing. New packaging options could provide an alternative.
Intel Inside The Package
Mark Bohr opens up on the company’s push into multi-chip solutions, and upcoming issues at 7nm and 5nm.
2.5D, FO-WLP Issues Come Into Focus
Advanced packaging goes mainstream, creating ripples throughout the back-end of the semiconductor industry.
Betting On Wafer-Level Fan-Outs
Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.
Electroplating IC Packages
Tooling challenges increase as advanced packaging ramps up.


realjjj says:

Isn’t IBM’s adjustable width nanosheet a bit of an advantage over FinFET?

Ed Sperling says:

IBM Research’s announcement is interesting, particularly because it can be manufactured using EUV. All of this stuff is still in the early development phase, though, so which one ultimately wins is unknown. (The details can be found here: https://www-03.ibm.com/press/us/en/pressrelease/52531.wss)

Mark LaPedus says:

A nanosheet is one form of a gate-all-around or nanowire FET. See Uncertainty Grows For 5nm, 3nm. https://semiengineering.com/uncertainty-grows-for-5nm-3nm/ Nanowire FETs are aimed for 5nm and/or 3nm. Samsung has already announced plans for a nanosheet FET at 4nm. https://news.samsung.com/global/samsung-set-to-lead-the-future-of-foundry-with-comprehensive-process-roadmap-down-to-4nm

Ian Dedic says:

Three nanosheets stacked one on top of the other look very like 3 FinFETs side by side, just rotated through 90 degrees. The nanosheet advantages may be the ability to vary the width (FinFETs are fixed height) and easier contacts to source/drain, the disadvantage may be the inability to do small low-power transistors — so maybe nanosheets are good for high-speed applications (which is why IBM like them), but not so good for high-density low-power applications. Time will tell which approach wins, I doubt if the industry can afford two radically different structures both from the point of view of process development cost as well as IP development cost.

realjjj says:

In the article IMEC doesn’t see the need for GAA but was wondering if they have factored in adjustable width in their modeling. Maybe they even see this is as an empty claim, some are skeptical.

Mark LaPedus says:

On the contrary, Imec is aggressively pushing for GAA. They FIRMLY believe the industry needs to move to GAA, whether that’s a traditional nanowire or nanosheet. They are leaning towards NWs. Imec sees a need at or near 40nm gate pitch

realjjj says:

I meant on foundry 5nm and that’s what is clearly stated in the interview, GAA doesn’t offer an advantage on the node in their opinion – seems they go with the line of thinking that the advantage is only about scaling.
Also wonder about analog folks, they might like the adjustable width.
Wire vs sheet, depends what you compare ( do you compare 8nm nanosheet width with 8nm diameter wire?), the markets one wants to address, the flexibility the foundry aims for with the process. W/e, i like TFET and monolithic3D LOL.

Mark LaPedus says:

Correct me if I’m wrong, but the foundry 5nm is a full-scaled 7nm. That’s finFETs. Samsung and TSMC are looking at looking at GAA at 4nm and 3nm, respectively.

realjjj says:

So you don’t think of this as 5nm foundry while I do and I assume GloFo will call it 5nm. Samsung calls it 4nm but that’s just marketing as it’s a second gen 5nm for them.

Marketing names aside, GloFo will evolve their 7nm but no way they can afford to invest in another major node before this GAA node.

Leave a Reply

(Note: This name will be displayed publicly)