Top Stories
Target: 50% Reduction In Memory Power
Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.
Low Power Meets Variability At 7/5nm
Reductions in voltage, margin and increases in physical effects are making timing closure and signoff much more difficult.
Optimization Challenges For Safety And Security
The road to optimized tradeoff automation is long. Changing attributes along the way can make it even more difficult.
Video
Multi-Physics At 5/3nm
Why process, voltage and temperature are so interrelated at future nodes, and what impact that has on design.
Blogs
Editor In Chief Ed Sperling digs into why power, performance and area are becoming increasingly difficult to balance, in More Memory And Processor Tradeoffs.
Mentor’s Harry Foster warns that increased design size is only one dimension of the growing complexity challenge, in The Weather Report: 2018 Study On IC/ASIC Verification Trends.
Rambus’ Frank Ferro looks at why memory choices for AI systems depend on the application, in GDDR6 And HBM2: Signal Integrity Challenges For AI.
Synopsys’ Ribhu Mittal explains why the length of tests, failure reproduction, and the sheer amount of data generated pose problems for emulation, in Exascale Emulation Debug Challenges.
Arm’s Paul Williamson argues that trusted, independent security testing is critical to enabling widespread deployment of IoT devices, in Taking Security-By-Design To The Next Level.
