Top Stories

Moving Data And Computing Closer Together
This is far from simple, but the power/performance and latency benefits are potentially huge.

Designing For Extreme Low Power
Power is becoming a differentiator in many designs, and for IoT and edge devices it may be the most important competitive differentiation.

Power Impact At The Physical Layer Causes Downstream Effects
PHYs have a growing impact on performance and power in both planar and multi-die designs.

Blogs

Rambus’ Frank Ferro explains why the memory developed for high-end graphics cards isn’t just for gaming anymore, in An Expanding Application Space For GDDR6 Memory.

Adesto’s Tommy Mullane advises that on big chips, tools to support communication are a critical factor in success, in Different Roles, Different Tools.

Cadence’s Thomas Wong lays out why, when it comes to die-to-die PHY interfaces, the best solution is highly dependent on the end application, in Enabling Cost-Effective, High-Performance Die-to-Die Connectivity.

Mentor’s Terence Chen and Alexander Volkov describe a way to add simplicity, predictability, and flexibility to the physical implementation process, in Easier Low Power ICs With Reference Flows.

The RIKEN Center’s Satoshi Matsuoka gives an insider’s view of the technology and collaboration between the new Arm-based supercomputer at RIKEN, in Building Fugaku, The World’s Fastest Supercomputer.

Moortec’s Tim Penhale-Jones spells out why getting at the truth of an SoC’s state calls for an impartial source of information, in ‘Speak No Evil’ And SoC Problems.

Ansys’ Peter Hallschmid and Dylan McGuire demonstrate a flow to design and optimize gain elements and lasers on indium phosphide and gallium arsenide, in Simulation Of Semiconductor Edge-Emitting Lasers.